International Processor Hardware Reference

TIMING
Memory Timing
508 Hardware Reference NS9215
SPI slave mode 0
and 1: 2-byte
transfer
Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel
B/A/C/D Control Register A.
SPI slave mode 2
and 3: 2-byte
transfer
Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel
B/A/C/D Control Register A.
MSB LSB MSB LSB
MSB LSB MSB LSB
SP6SP4
SP8SP7
S10SP5SP1
S9SP12SP12SP13SP 13SP3SP0
SPI CLK Out (Mode 0)
SPI CLK Out (Mode 1)
SPI Enable
SPI Data Out
SPI Data In
MS B LSB MS B LSB
MS B LSB MS B LSB
SP6SP4
SP 8SP7
S10SP5SP1
S9SP3SP 0
SPI CLK Out (Mode 2)
SPI CLK Out (Mode 3)
SPI Enable
SP I Data Out
SP I Data I n