NS9750 Hardware Reference 90000624_G
NS9750 Hardware Reference Part number/version: 90000624_G Release date: March 2008 www.digiembedded.
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Contents C h a p t e r 1 : A b o u t N S 9 7 5 0 ............................................................................................... 1 NS9750 Features ......................................................................... 2 System-level interfaces................................................................. 8 System boot ............................................................................. 10 Reset....................................................................................
C h a p t e r 3 : W o r k i n g w i t h t h e C P U ......................................................................47 About the processor .................................................................... 48 Instruction sets.......................................................................... 49 ARM instruction set .............................................................. 50 Thumb instruction set........................................................... 50 Java instruction set ..........
TLB structure ....................................................................104 Caches and write buffer ..............................................................105 Cache features ..................................................................105 Write buffer .....................................................................106 Enabling the caches ............................................................107 Cache MVA and Set/Way formats ............................................
Interrupt Status Raw ...........................................................152 Timer Interrupt Status register ...............................................153 Software Watchdog Configuration register .................................153 Software Watchdog Timer register ..........................................155 Clock Configuration register ..................................................155 Reset and Sleep Control register .............................................
Dynamic memory controller .........................................................224 Write protection ................................................................224 Access sequencing and memory width ......................................224 Address mapping ................................................................225 Registers ................................................................................264 Register map ....................................................................
Overview ................................................................................316 Ethernet MAC...........................................................................317 Station address logic (SAL) ....................................................321 Statistics module ...............................................................321 Ethernet front-end module ..........................................................323 Receive packet processor ..............................................
RX_D Buffer Descriptor Pointer register ....................................384 Ethernet Interrupt Status register ...........................................385 Ethernet Interrupt Enable register...........................................387 TX Buffer Descriptor Pointer register........................................389 Transmit Recover Buffer Descriptor Pointer register .....................389 TX Error Buffer Descriptor Pointer register.................................
CardBus interrupts..............................................................465 C h a p t e r 8 : B B u s B r i d g e ................................................................................................467 BBus bridge functions .................................................................468 Bridge control logic ...................................................................469 DMA accesses ....................................................................471 BBus control logic ...
DMA buffer descriptor ................................................................504 DMA channel assignments ............................................................509 DMA Control and Status registers ...................................................510 DMA Buffer Descriptor Pointer................................................512 DMA Control register ...........................................................514 DMA Status/Interrupt Enable register .......................................
Flow charts .............................................................................556 Master module (normal mode, 16-bit).......................................556 Slave module (normal mode, 16-bit) ........................................557 C h a p t e r 1 2 : L C D C o n t r o l l e r ....................................................................................559 LCD features............................................................................560 Programmable parameters ............
LCDPalette register.............................................................595 Interrupts ...............................................................................598 MBERRORINTR — Master bus error interrupt................................598 VCOMPINTR — Vertical compare interrupt..................................598 LBUINTR — Next base address update interrupt ...........................599 C h a p t e r 1 3 : S e r i a l C o n t r o l M o d u l e : U A R T ......................................
Serial port control and status registers ............................................650 Serial Channel B/A/C/D Control Register A ................................652 Serial Channel B/A/C/D Control Register B ................................655 Serial Channel B/A/C/D Status Register A ..................................657 Serial Channel B/A/C/D Bit-rate register ...................................660 Serial Channel B/A/C/D FIFO Data register ................................
Pin Interrupt Mask register ....................................................700 Pin Interrupt Control register.................................................701 Granularity Count register ....................................................702 Forward Address register ......................................................703 Core Phase (IEEE1284) register ...............................................704 C h a p t e r 1 6 : U S B C o n t r o l l e r M o d u l e .......................................
HcHCCA register ................................................................739 HcPeriodCurrentED register ...................................................740 HcControlHeadED register.....................................................741 HcControlCurrentED register..................................................742 HcBulkHeadED register ........................................................743 HcBulkCurrentED register .....................................................744 HcDoneHead register.
Memory timing .........................................................................795 SDRAM burst read (16-bit) .....................................................796 SDRAM burst read (16-bit), CAS latency = 3 ................................797 SDRAM burst write (16-bit) ....................................................798 SDRAM burst read (32-bit) .....................................................799 SDRAM burst read (32-bit), CAS latency = 3 ................................
SPI SPI SPI SPI master mode 0 and 1: 2-byte transfer ..................................829 master mode 2 and 3: 2-byte transfer ..................................829 slave mode 0 and 1: 2-byte transfer ....................................830 slave mode 2 and 3: 2-byte transfer ....................................830 IEEE 1284 timing .......................................................................831 IEEE 1284 timing example .....................................................831 USB timing .......
Using This Guide R eview this section for basic information about the guide you are using, as well as general support and contact information. This printed version of the NS9750 Hardware Reference, Rev. E includes two volumes (90000622_E and 90000623_E). A single PDF (90000624_E) is included on your documentation CD. About this guide This guide provides information about the Digi NS9750, a single chip 0.13μm CMOS network-attached processor. The NS9750 is part of the Digi NET+ARM family of devices.
What’s in this guide This table shows where you can find specific information in the printed guides.
Conventions used in this guide This table describes the typographic conventions used in this guide: This convention Is used for italic type Emphasis, new terms, variables, and document titles. monospaced type Filenames, pathnames, and code examples. _ (underscore) Defines a signal as being active low.
Be aware that if you see differences between the documentation you received in your package and the documentation on the Web site, the Web site content is the latest version. Customer support To get help with a question or technical problem with this product, or to make comments and recommendations about our products or documentation, use the contact information listed in this table: xxii For Contact information Technical support United States: +1 877 912-3444 Other locations: +1 952 912-3444 www.
About NS9750 C H A P T E R 1 T he Digi NS9750 is a single chip 0.13μm CMOS network-attached processor. This chapter provides an overview of the NS9750, which is based on the standard architecture in the NET+ARM family of devices.
NS9750 Features NS9750 Features The NS9750 uses an ARM926EJ-S core as its CPU, with MMU, DSP extensions, Jazelle Java accelerator, and 8 kB of instruction cache and 4 kB of data cache in a Harvard architecture. The NS9750 runs up to 200 MHz, with a 100 MHz system and memory bus and 50 MHz peripheral bus. The NS9750 offers an extensive set of I/O interfaces and Ethernet high-speed performance and processing capacity.
About NS9750 Burst mode support with automatic data width adjustment Two external DMA channels for external peripheral support System Boot High-speed boot from 8-bit, 16-bit, or 32-bit ROM or Flash Hardware-supported low cost boot from serial EEPROM through SPI port (patent pending) High performance 10/100 Ethernet MAC 10/100 Mbps MII/RMII PHY interfaces Full-duplex or half-duplex Station, broadcast, or multicast address filtering 2 kB RX FIFO 256-byte TX FIFO with on-chip buffer descriptor ring – Elimi
NS9750 Features Flexible LCD controller Supports most commercially available displays: – Active Matrix color TFT displays: Up to 24bpp direct 8:8:8 RGB; 16 colors – Single and dual panel color STN displays: Up to 16bpp 4:4:4 RGB; 3375 colors – Single and dual panel monochrome STN displays: 1, 2, 4bpp palettized gray scale Formats image data and generates timing control signals Internal programmable palette LUT and grayscaler support different color techniques Programmable panel-clock frequency USB p
About NS9750 Internal or external clock support, digital PLL for RX clock extraction 4 receive-side data match detectors 2 dedicated DMA channels per module, 8 channels total 32 byte TX FIFO and 32 byte RX FIFO per module I2C port I2C v.1.
NS9750 Features Each DMA channel supports memory-to-memory transfers Power management (patent pending) Power save during normal operation – Disables unused modules Power save during sleep mode – Sets memory controller to refresh – Disables all modules except selected wakeup modules – Wakeup on valid packets or characters Vector interrupt controller Decreased bus traffic and rapid interrupt service Hardware interrupt prioritization General purpose timers/counters 16 independent 16-bit or 32-bit p
About NS9750 External interrupts 4 external programmable interrupts – Rising or falling edge-sensitive – Low level- or high level-sensitive Clock generator Low cost external crystal On-chip phase locked loop (PLL) Software programmable PLL parameters Optional external oscillator Separate PLL for USB Operating grades/Ambient temperatures 200 MHz: 0 – 70o C 162 MHz: -40 – +85o C 125 MHz: 0 – 70o C www.digiembedded.
System-level interfaces System-level interfaces Figure 1 shows the NS9750 system-level interfaces. I2C JTAG USB Host or Dev ice Ethernet USB Host control Controls Serial 1284 NS9750 Data LCD GPIO Sy stem Memory Address Ext. DMA Ext.
About NS9750 – 1284 port – Up to 24-bit TFT or STN color and monochrome LCD controller – Two external DMA channels – Four external interrupt pins programmed to rising or falling edge, or to high or low level – Sixteen 16-bit or 32-bit programmable timers or counters – Two control signals to support USB host JTAG development interface Clock interfaces for crystal or external oscillator – System clock – USB clock Clock interface for optional LCD external oscillator Power and ground www.
System boot System boot There are two ways to boot the NS9750 system (see Figure 2): From a fast Flash over the system memory bus From an inexpensive, but slower, serial EEPROM through SPI port B. Both boot methods are glueless. The bootstrap pin, RESET_DONE, indicates where to boot on a system powerup. Flash boot can be done from 8-bit, 16-bit, or 32-bit ROM or Flash. Serial EEPROM boot is supported by NS9750 hardware.
About NS9750 input reset pin can be driven by a system reset circuit or a simple power-on reset circuit. RESET_DONE as an input Used at bootup only: When set to 0, the system boots from SDRAM through the serial SPI EEPROM. When set to 1, the system boots from Flash/ROM. This is the default. RESET_DONE as an output Sets to 1, per Step 6 in the boot sequence.
Reset Figure 3 shows a sample reset circuit. RESET delay required following valid power applied to the NS9750 to allow clock circuits to stabilize. U6 3R3V 3 RST- 2 GND 1 RESETn RESET_ VCC MAX809S_SOT23D NS9750 C14 100nF RESET_DONE RESET_DONE Adding R5 will enable BOOT from Serial EE memory connected to SPI port B to SDRAM located on dy_cs_n[0]. RESET_DONE remains “LOW” until BOOT is completed. RESET_DONE = 1 indicates that the CPU is ready.
About NS9750 Hardware reset duration is 4 ms for PLL to stabilize. Software duration depends on speed grade, as shown in Table 1. Speed grade CPU clock cycles Duration 200 MHz 128 640 ns 162 MHz 128 790 ns 125 MHz 128 1024 ns Table 1: Software reset duration The minimum reset pulse width is 10 crystal clocks. System clock The system clock is provided to the NS9750 by either a crystal or an external oscillator. Table 2 shows sample clock frequency settings for each chip speed grade.
System clock Add R10 to bypass SYS PLL R10 S_PLL_BP_ X1_SYS_OSC is qualified for an external LVTTL clock up to 400 MHz in PLL bypass mode. The system PLL is bypassed by pulling down GPIO19. In PLL bypass mode, the ARM9 CPU is ½ the frequency of X!_SYS_OSC. GPIO19_PLL_BP 2R4K R11 100 When the PLL is enabled, the clock input range is 20 - 40 MHz.
About NS9750 USB clock USB is clocked by a separate PLL driven by an external 48 MHz crystal, or it can be driven directly by an external 48 MHz oscillator. 3R3V TB1 Y1_PWR BEAD_0805_601 C9 100nF Y1 4 2 1 VCC GND TEST R6 OUT 3 Y1_OUT X1_USB X1_USB_OSC 100 EC2600_TTS_48M NS9750 L4 ** 1uH_5% NOTE: ** = OPTIONAL Crystal circuit X1_IN TANK_LC R9 ** X2_USB R8 ** 1.5M X2_USB_OSC 100 OHM 1 2 ** C16 100pF_5% TANK_RC R7 ** 68R1 Tank Circuit 4 3 48.
NS9750 Pinout C H A P T E R 2 T he NS9750 offers a connection to an external bus expansion module, as well as a glueless connection to SDRAM, PC100 DIMM, flash, EEPROM, and SRAM memories, and an external bus expansion module. It includes a versatile embedded LCD controller, a PCI/CardBus port, a USB port, and four multi-function serial ports. The NS9750 provides up to 50 general purpose I/O (GPIO) pins and configurable power management with sleep mode.
Pinout and signal descriptions Pinout and signal descriptions Each pinout table applies to a specific interface, and contains the following information: Heading Description Pin # Pin number assignment for a specific I/O signal Signal Pin name for each I/O signal. Some signals have multiple function modes and are identified accordingly. The mode is configured through firmware using one or more configuration registers. _n in the signal name indicates that this signal is active low.
NS9750 Pinout OD (mA) I/O Description addr[5] 8 O Address bus signal A19 addr[6] 8 O Address bus signal A17 addr[7] 8 O Address bus signal C16 addr[8] 8 O Address bus signal B16 addr[9] 8 O Address bus signal A16 addr[10] 8 O Address bus signal D15 addr[11] 8 O Address bus signal C15 addr[12] 8 O Address bus signal B15 addr[13] 8 O Address bus signal A15 addr[14] 8 O Address bus signal C14 addr[15] 8 O Address bus signal B14 addr[16] 8 O Address
Pinout and signal descriptions OD (mA) I/O Description clk_en[3] 8 O SDRAM clock enable A10 clk_out[0] 8 O SDRAM reference clock. Connect to clk_in[0] using series termination.
NS9750 Pinout OD (mA) I/O Description data[21] 8 I/O Data bus signal C22 data[22] 8 I/O Data bus signal D21 data[23] 8 I/O Data bus signal B23 data[24] 8 I/O Data bus signal A24 data[25] 8 I/O Data bus signal A23 data[26] 8 I/O Data bus signal B22 data[27] 8 I/O Data bus signal C21 data[28] 8 I/O Data bus signal A22 data[29] 8 I/O Data bus signal B21 data[30] 8 I/O Data bus signal C20 data[31] 8 I/O Data bus signal E1 data_mask[0] 8 O SDRAM data
Pinout and signal descriptions OD (mA) I/O Description dy_cs_n[0] 8 O SDRAM chip select signal B8 dy_cs_n[1] 8 O SDRAM chip select signal A6 dy_cs_n[2] 8 O SDRAM chip select signal C7 dy_cs_n[3] 8 O SDRAM chip select signal C6 st_oe_n 8 O Static memory output enable D6 ras_n 8 O SDRAM row address strobe H1 dy_pwr_n 8 O SyncFlash power down B10 st_cs_n[0] 8 O Static memory chip select signal C10 st_cs_n[1] 8 O Static memory chip select signal B9 st_cs_n[2] 8
NS9750 Pinout Name I/O Description clk_en[3:0] O SDRAM clock enable. Used for SDRAM devices. Note: The clk_en signals are associated with the dy_cs_n signals. Connect SDRAM clock enables directly to a 3.3V or pullup resistor to avoid an SDRAM lockup condition during a manual or brownout condition reset.
Pinout and signal descriptions Figure 6 shows NS9750 SDRAM clock termination. All series termination resistors must be placed close to driver clk_out[0] clk_in[0] CLK_IN[0] NS9750 clk_out[1] Always connect clk_out[0] to clk_in[0] using series termination. Must not drive any SDRAM loads. Data in from SDRAMs is sampled on the rising edge of this clock. This trace can be a loop 2 to 3 inches in length. Read Data clock will be delayed 180pS/per inch.
NS9750 Pinout clk_en[n] U1 0 = B0 TO A S 6 reset_done 3.3V 5 V+ 2 1 B1 4 A GND 3.3V B0 2.
Pinout and signal descriptions Signal name Pin # MII RMII U3 rxd[1] rxd[1] U2 rxd[2] U1 OD (mA) U/D Description I/O MII RMII I Receive data bit 1 Receive data bit 1 N/C I Receive data bit 2 Pull low external to NS9750 rxd[3] N/C I Receive data bit 3 Pull low external to NS9750 V3 tx_clk N/C I Transmit clock Pull low external to NS9750 AA1 tx_en tx_en 2 O Transmit enable Transmit enable Y3 tx_er N/C 2 O Transmit error N/A Y2 txd[0] txd[0] 2 O Transmit data
NS9750 Pinout Pin # Signal name AD20 U/D OD (mA) I/O Description bist_en_n I Enable internal BIST operation AF21 pll_test_n I Enable PLL testing AE21 scan_en_n I Enable internal scan testing B18 sys_pll_dvdd System clock PLL 1.5V digital power A18 sys_pll_dvss System clock PLL digital ground B17 sys_pll_avdd System clock PLL 3.
Pinout and signal descriptions bist_en_n, pll_test_n, and scan_en_n Table 7 is a truth/termination table for bist_en_n, pll_test_n, and scan_en_n. Normal operation ARM debug pll_test_n pull up pull up 10K recommended bist_en_n pull down pull up 10K pullup = debug 2.4K pulldown = normal scan_en_n pull down pull down 2.
NS9750 Pinout OD (mA) I/O Description ad[12]1 N/A I/O PCI time-multiplexed address/data bus N25 ad[13]1 N/A I/O PCI time-multiplexed address/data bus N26 1 ad[14] N/A I/O PCI time-multiplexed address/data bus P26 ad[15]1 N/A I/O PCI time-multiplexed address/data bus U24 1 ad[16] N/A I/O PCI time-multiplexed address/data bus V26 ad[17]1 N/A I/O PCI time-multiplexed address/data bus V25 ad[18]1 N/A I/O PCI time-multiplexed address/data bus W26 ad[19]1 N/A I/O PCI ti
Pinout and signal descriptions Pin # Signal name Y25 idsel3, 4 U/D OD (mA) I/O Description N/A I Initialization device select: For PCI host applications, connect to AD11. For PCI device applications, connection is determined by the PCI device number assigned to the NS9750. For CardBus applications, connect to the external pullup resistor. Do not allow input to float in any application.
NS9750 Pinout OD (mA) I/O Description pci_int_d_n2 N/A I PCI interrupt request D AE26 pci_reset_n3 N/A I/O PCI reset, output if internal central resource enabled AB24 pci_clk_in N/A I PCI clock in. (Connected to pci_clk_out or an externally generated PCI reference clock.) AA23 pci_clk_out N/A O PCI clock out Pin # Signal name AD22 U/D U Table 8: PCI interface pinout PCI/CardBus signals Most of the CardBus signals are the same as the PCI signals.
Pinout and signal descriptions PCI signal CardBus signal CardBus type Description GNT2# CVS1 Output Voltage sense pin. Normally driven low by NS9750, but toggled during the interrogation of the external CardBus device to find voltage requirements. Note: Do not connect directly to the CardBus connector. See the diagram "CardBus system connections to NS9750" on page 462 for a suggested connection scheme. GNT3# CVS2 Output Voltage sense pin.
NS9750 Pinout 3.3V U1D PCI R2 10K PCI_VB R3 10K L25 P25 U25 AA26 DEVSELR4 10K FRAMER5 10K TRDYR6 10K IRDY- T26 U26 Y25 T25 T24 AC24 AD23 AE24 AD25 AB23 AC22 AF25 AF24 AE23 AD22 AE26 R7 10K PERRR8 10K STOP- R25 P24 R26 R24 AF23 Notes: 1. Startup code needs to put the PCI bridge into reset.
Pinout and signal descriptions GPIO MUX The BBus utility contains the control pins for each GPIO MUX bit. Each pin can be selected individually; that is, you can select any option (00, 01, 02, 03) for any pin, by setting the appropriate bit in the appropriate register. Some signals are muxed to two different GPIO pins, to maximize the number of possible applications. These duplicate signals are marked as such in the Descriptions column in the table.
NS9750 Pinout Pin # Signal name U/D OD (mA) I/O Description (4 options: 00, 01, 02, 03) AE17 gpio[4]1 U 2 I/O 00 01 02 03 Ser port B DTR 1284 busy (peripheral-driven) DMA ch 1 done GPIO 4 AF17 gpio[5] U 2 I/O 00 01 02 03 Ser port B DSR 1284 PError (peripheral-driven) DMA ch 1 read enable GPIO 5 AD16 gpio[6] U 2 I/O 00 01 02 03 Ser port B RI / SPI port B clk 1284 nFault (peripheral-driven)3 Timer 7 (duplicate) GPIO 6 AE16 gpio[7] U 2 I/O 00 01 02 03 Ser port B DCD / SPI port
Pinout and signal descriptions Pin # Signal name U/D OD (mA) I/O Description (4 options: 00, 01, 02, 03) AE14 gpio[12]1 U 2 I/O 00 01 02 03 Ser port A DTR Reserved Reserved GPIO 12 AF14 gpio[13] U 2 I/O 00 01 02 03 Ser port A DSR Ext IRQ 0 (duplicate) Timer 10 (duplicate) GPIO 13 AF13 gpio[14] U 2 I/O 00 01 02 03 Ser port A RI / SPI port A clk Timer 1 Reserved GPIO 14 AE13 gpio[15] U 2 I/O 00 01 02 03 Ser port A DCD / SPI port A enable Timer 2 Reserved GPIO 15 AD13 gpio[1
NS9750 Pinout Pin # Signal name U/D OD (mA) I/O Description (4 options: 00, 01, 02, 03) AC12 gpio[20]1 U 8 I/O 00 01 02 03 Ser port C DTR LCD clock Reserved GPIO 20 AF11 gpio[21] U 4 I/O 00 01 02 03 Ser port C DSR LCD frame pulse-vert Reserved GPIO 21 AE11 gpio[22] U 4 I/O 00 01 02 03 Ser port C RI / SPI port C clk LCD AC bias-data enable Reserved GPIO 22 AD11 gpio[23] U 4 I/O 00 01 02 03 Ser port C DCD / SPI port C enable LCD line end Timer 14 (duplicate) GPIO 23 AF10 gp
Pinout and signal descriptions Pin # Signal name U/D OD (mA) I/O Description (4 options: 00, 01, 02, 03) AE9 gpio[28] U 4 I/O 00 01 02 03 Ext IRQ 1 (duplicate) LCD data bit 4 LDC data bit 8 (duplicate) GPIO 28 AF8 gpio[29] U 4 I/O 00 01 02 03 Timer 5 LCD data bit 5 LCD data bit 9 (duplicate) GPIO 29 AD9 gpio[30] U 4 I/O 00 01 02 03 Timer 6 LCD data bit 6 LCD data bit 10 (duplicate) GPIO 30 AE8 gpio[31] U 4 I/O 00 01 02 03 Timer 7 LCD data bit 7 LCD data bit 11 (duplicate) G
NS9750 Pinout Pin # Signal name U/D OD (mA) I/O Description (4 options: 00, 01, 02, 03) AF5 gpio[36] U 4 I/O 00 01 02 03 Reserved 1284 Data 5 (bidirectional) LCD data bit 12 GPIO 36 AD6 gpio[37] U 4 I/O 00 01 02 03 Reserved 1284 Data 6 (bidirectional) LCD data bit 13 GPIO 37 AE5 gpio[38] U 4 I/O 00 01 02 03 Reserved 1284 Data 7 (bidirectional) LCD data bit 14 GPIO 38 AF4 gpio[39] U 4 I/O 00 01 02 03 Reserved 1284 Data 8 (bidirectional) LCD data bit 15 GPIO 39 AC6 gpio[40]
Pinout and signal descriptions Pin # Signal name U/D OD (mA) I/O Description (4 options: 00, 01, 02, 03) AD2 gpio[44]1 U 4 I/O 00 01 02 03 Ser port D TxData / SPI port D dout 1284 Select (peripheral-driven) LCD data bit 20 GPIO 44 AE1 gpio[45] U 4 I/O 00 01 02 03 Ser port D RxData / SPI port D din 1284 nStrobe (host-driven) LCD data bit 21 GPIO 45 AB3 gpio[46] U 4 I/O 00 01 02 03 Ser port D RTS 1284 nAutoFd (host-driven) LCD data bit 22 GPIO 46 AA4 gpio[47] U 4 I/O 00 01 02
NS9750 Pinout Pin # Signal name U/D OD (mA) I/O Description (4 options: 00, 01, 02, 03) 2 gpio[17] is used as both a bootstrap input pin for PLL_ND and an output that controls a power switch for USB Host power. If the power switch needs to powerup in the inactive state, the enable to the power switch must be the same value as the bootstrap value for PLL_ND; for example, if PLL_ND requires high on gpio[17], a high true power switch must be selected.
Pinout and signal descriptions LCD module signals The LCD module signals are multiplexed with GPIO pins. They include seven control signals and up to 24 data signals. Table 11 describes the control signals.
NS9750 Pinout I 2 C interface OD (mA) I/O Description iic_scl 4 I/O I2C serial clock line. Add a 10K resistor to VDDA(3.3V) if not used. iic_sda 4 I/O I2C serial data line. Add a 10K resistor to VDDA(3.3V) if not used. Bits Signal name AC15 AF16 U/D Table 12: I 2C interface pinout USB interface Notes: If not using the USB interface, these pins should be pulled down to ground through a 15K ohm resistor. All output drivers for USB meet the standard USB driver specification.
Pinout and signal descriptions OD (mA) I/O Description 2 O Test data out U I Test mode select trst_n U I Test mode reset rtck U I/O Returned test clock, ARM core only Bits Signal name AE19 tdo AC18 tms AF20 AD19 U/D 2 Table 14: JTAG interface/boundary scan pinout 3.3V R1 2.4K ## P1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 HEADER 10X2.1SP JP1 recommended instead of R9 during development phase, JP1 ** NS9750_BGA352 10K H25 R10 2.
NS9750 Pinout Reserved Pin# Description J1 Tie to ground directly K3 Tie to ground directly K2 Tie to ground directly K1 Tie to ground directly R1 Tie to ground directly R2 Tie to ground directly R3 Tie to ground directly T1 Tie to ground directly AF6 Tie to ground directly AE3 Tie to ground directly AC5 Tie to ground directly AD4 Tie to 1.5V core power AF2 Tie to 3.
Pinout and signal descriptions Power ground Pin # Signal name Description J23, L23, K23, U23, T23, V23, D18, D17, AC17, D16, AC16, D11, D10, AC11, AC10, AC9, J4, L4, K4, U4, T4, V4 VDDC Core power, 1.5V G23, H23, M23, R23, P23, N23, Y23, W23, D20, AC20, D19, AC19, D14, D13, AC14, AC13, D8, D7, AC8, AC7, G4, H4, M4, R4, P4, N4, Y4, W4 VDDS I/O power, 3.
Working with the CPU C H A P T E R 3 T he NS9750 core is based on the ARM926EJ-S processor. The ARM926EJ-S processor belongs to the ARM9 family of general-purpose microprocessors. The ARM926EJ-S processor is targeted at multi-tasking applications in which full memory management, high performance, low die size, and low power are important.
About the processor About the processor The ARM926EJ-S processor supports the 32-bit ARM and 16-bit Thumb instructions sets, allowing you to trade off between high performance and high code density. The processor includes features for efficient execution of Java byte codes, providing Java performance similar to JIT but without the associated overhead. The ARM926EJ-S supports the ARM debug architecture, and includes logic to assist in both hardware and software debug.
Working with the CPU Figure 10 shows the main blocks in the ARM926EJ-S processor.
Instruction sets ARM instruction set The ARM instruction set allows a program to achieve maximum performance with the minimum number of instructions. The majority of instructions are executed in a single cycle. Thumb instruction set The Thumb instruction set is simpler than the ARM instruction set, and offers increased code density for code that does not require maximum performance. Code can switch between ARM and Thumb instruction sets on any procedure call.
Working with the CPU System control processor (CP15) registers The system control processor (CP15) registers configure and control most of the options in the ARM926EJ-S processor. Access the CP15 registers using only the MRC and MCR instructions in a privileged mode; the instructions are provided in the explanation of each applicable register. Using other instructions, or MRC and MCR in unprivileged mode, results in an UNDEFINED instruction exception.
System control processor (CP15) registers Accessing CP15 registers Use only MRC and MCR instructions, only in privileged mode, to access CP15 registers. Figure 11 shows the MRC and MCR instruction bit pattern.
Working with the CPU Term Abbreviation Description UNDEFINED UND An instruction that accesses CP15 in the manner indicated takes the UNDEFINED instruction exception. SHOULD BE ZERO SBZ When writing to this field, all bits of the field SHOULD BE ZERO. SHOULD BE ONE SBO When writing to this location, all bits in this field SHOULD BE ONE.
System control processor (CP15) registers Register Reads Writes 4 Reserved Reserved 5 Data fault status (based on opcode_2 value) Data fault status (based on opcode_2 value) 6 Instruction fault status (based on opcode_2 value) Instruction fault status (based on opcode_2 value) 7 Cache operations Cache operations 8 Unpredictable TLB 9 Cache lockdown (based on CRm value) Cache lockdown 10 TLB lockdown TLB lockdown 11 and 12 Reserved Reserved 13 FCSE PID (based on opcode_2 value) F
Working with the CPU R0: ID code and cache type status registers Register R0 access the ID register, and cache type register. Reading from R0 returns the device ID, and the cache type, depending on the opcode_2 value: opcode_2=0 ID value opcode_2=1 instruction and data cache type The CRm field SHOULD BE ZERO when reading from these registers. Table 19 shows the instructions you can use to read register R0.
System control processor (CP15) registers R0: Cache type register R0: Cache type is a read-only register that contains information about the size and architecture of the instruction cache (ICache) and data cache (DCache) enabling operating systems to establish how to perform operations such as cache cleaning and lockdown. See "Cache features" on page 105 for more information about cache. You can access the cache type register by reading CP15 register R0 with the opcode_2 field set to 1.
Working with the CPU Dsize and Isize fields The Dsize and Isize fields in the cache type register have the same format, as shown: 11 10 9 0 0 6 5 Size 3 2 1 Assoc M 0 Len The field contains these bits: Field Description Size Determines the cache size in conjunction with the M bit. The M bit is 0 for DCache and ICache. The size field is bits [21:18] for the DCache and bits [9:6] for the ICache. The minimum size of each cache is 4 KB; the maximum size is 128 KB.
System control processor (CP15) registers R1: Control register Register R1 is the control register for the ARM926EJ-S processor. This register specifies the configuration used to enable and disable the caches and MMU (memory management unit). It is recommended that you access this register using a readmodify-write sequence. For both reading and writing, the CRm and opcode_2 fields SHOULD BE ZERO.
Working with the CPU Bits Name Function [15] L4 Determines whether the T is set when load instructions change the PC.
System control processor (CP15) registers Bits Name Function [0] M bit MMU enable/disable 0 Disabled 1 Enabled Table 22: R1: Control register bit definition The M, C, I, and RR bits directly affect ICache and DCache behavior, as shown: Cache MMU Behavior ICache disabled Enabled or disabled All instruction fetches are from external memory (AHB). ICache enabled Disabled All instruction fetches are cachable, with no protection checking. All addresses are flat-mapped; that is: VA=MVA=PA.
Working with the CPU R2: Translation Table Base register Register R2 is the Translation Table Base register (TTBR), for the base address of the first-level translation table. Reading from R2 returns the pointer to the currently active first-level translation table in bits [31:14] and an UNPREDICTABLE value in bits [13:0]. Writing to R2 updates the pointer to the first-level translation table from the value in bits[31:14] of the written value. Bits [13:0] SHOULD BE ZERO.
System control processor (CP15) registers Each two-bit field defines the access permissions for one of the 16 domains (D15–D0): 00 01 10 11 No access: Any access generates a domain fault Client: Accesses are checked against the access permission bits in the section or page descriptor Reserved: Currently behaves like no access mode (00) Manager: Accesses are not checked against the access permission bits, so a permission fault cannot be generated.
Working with the CPU Figure 16 shows the format of the Fault Status registers. Table 24 describes the Fault Status register bits. 31 9 UNP/SBZ 8 0 7 4 3 Domain 0 Status Figure 16: Fault Status registers format Bits Description [31:9] UNPREDICTABLE/SHOULD BE ZERO [8] Always reads as zero. Writes are ignored. [7:4] Specifies which of the 16 domains (D15–D0) was being accessed when a data fault occurred. [3:0] Type of fault generated.
System control processor (CP15) registers Priority Source Size Status Domain Lowest External abort Section page 0b1000 0b1010 Valid Valid Table 25: Fault Status register status field encoding R6: Fault Address register Register R6 accesses the Fault Address register (FAR). The Fault Address register contains the modified virtual address of the access attempted when a data abort occurred.
Working with the CPU Function Description Invalidate cache Invalidates all cache data, including any dirty data. Invalidate single entry using either index or modified virtual address Invalidates a single cache line, discarding any dirty data. Clean single data entry using either index or modified virtual address Writes the specified DCache line to main memory if the line is marked valid and dirty. The line is marked as not dirty, and the valid bit is unchanged.
System control processor (CP15) registers Function Description Wait for interrupt Drains the contents of the write buffers, puts the processor into low-power state, and stops the processor from executing further instructions until an interrupt (or debug request) occurs. When an interrupt does occur, the MCR instruction completes, and the IRQ or FIRQ handler is entered as normal.
Working with the CPU Figure 17 shows the modified virtual address format for Rd for the CP15 R7 MCR operations. The tag, set, and word fields define the MVA. For all cache operations, the word field SHOULD BE ZERO. 31 S+5 S+4 5 4 Set(=index) Tag 2 1 Word 0 SBZ Figure 17: R7: MVA format Figure 18 shows the Set/Way format for Rd for the CP15 R7 MCR operations. A and S are the base-two logarithms of the associativity and the number of sets. The set, way, and word files define the format.
System control processor (CP15) registers found, one of those lines is cleaned. The test and clean DCache instruction also returns the status of the entire DCache in bit 30. Note: The test and clean DCache instruction MRC p15, 0, r15, c7, c10, 3 is a special encoding that uses r15 as a destination operand. The PC is not changed by using this instruction, however. This MRC instruction also sets the condition code flags. If the cache contains any dirty lines, bit 30 is set to 0.
Working with the CPU Operation Data Instruction Invalidate set-associative TLB SBZ MCR p15, 0, Rd, c8, c7, 0 Invalidate single entry SBZ MCR p15, 0, Rd, c8, c7.
System control processor (CP15) registers These registers allow you to control which cache-ways of the four-way cache are used for the allocation on a linefill. When the registers are defined, subsequent linefills are placed only in the specified target cache way. This gives you some control over the cache pollution cause by particular applications, and provides a traditional lockdown operation for locking critical code into the cache.
Working with the CPU This sequence sets the L bit to 1 for way 0 of the ICache. Figure 20 shows the format for the Cache Lockdown register. 31 16 15 SBZ/UNP 4 SB0 3 0 L bits (cache ways 0 to 3) Figure 20: R9: Cache Lockdown register format Table 30 shows the format of the Cache Lockdown register L bits. All cache ways are available for allocation from reset.
System control processor (CP15) registers Specific loading of addresses into a cache-way The procedure to lock down code and data into way i of cache, with N ways, using format C, makes it impossible to allocate to any cache way other than the target cache way: 1 Be sure that no processor exceptions can occur during the execution of this procedure; for example, disable interrupts.
Working with the CPU Cache unlock procedure To unlock the locked down portion of the cache, write to Cache Lockdown register (R9) setting L==0 for the appropriate bit.
System control processor (CP15) registers See "R8:TLB Operations register" on page 68 for a description of the TLB-invalidate operations. Use these instructions to program the TLB Lockdown register: Function Instruction Read data TLB lockdown victim MRC p15, 0, Rd, c10, c0, 0 Write data TLB lockdown victim MCR p15, 0, Rd, c10, c0, 0 The victim automatically increments after any table walk that results in an entry being written into the lockdown part of the TLB.
Working with the CPU R13: Process ID register The Process ID register accesses the process identifier registers. The register accessed depends on the value on the opcode_2 field: opcode_2=0 Selects the Fast Context Switch Extension (FCSE) Process Identifier (PID) register. opcode_2=1 Selects the context ID register. Use the Process ID register to determine the process that is currently running. The process identifier is set to 0 at reset.
System control processor (CP15) registers Figure 22 shows the format of the FCSE PID register. 31 25 24 0 SBZ FCSE PID Figure 22: Process ID register format Performing a fast context switch You can perform a fast context switch by writing to the Process ID register (R13) with opcode_2 set to 0. The contents of the caches and the TLB do not have to be flushed after a fast context switch because they still hold address tags.
Working with the CPU Figure 23 shows the format of the Context ID register (Rd) transferred during this operation. 31 0 Context identifier Figure 23: Context ID register format R14 register Accessing (reading or writing) this register is reserved. R15: Test and debug register Register R15 to provides device-specific test and debug operations in ARM926EJ-S processors. Use of this register currently is reserved.
DSP DSP The ARM926EJ-S processor core provides enhanced DSP capability. Multiply instructions are processed using a single cycle 32x16 implementation. There are 32x32, 32x16, and 16x16 multiply instructions, or Multiply Accumulate (MAC), and the pipeline allows one multiply to start each cycle.
Working with the CPU Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions). Hardware page table walks. Invalidate entire TLB using R8: TLB Operations register (see "R8:TLB Operations register" on page 68). Invalidate TLB entry selected by MVA, using R8: TLB Operations register (see "R8:TLB Operations register" on page 68). Lockdown of TLB entries using R10: TLB Lockdown register (see "R10: TLB Lockdown register" on page 73).
Memory Management Unit (MMU) Access is permitted and an off-chip access is not required — the cache services the access. Access is not permitted — the MMU signals the CPU core to abort. If the TLB misses (it does not contain an entry for the MVA), the translation table walk hardware is invoked to retrieve the translation information from a translation table in physical memory. When retrieved, the translation information is written into the TLB, possible overwriting an existing value.
Working with the CPU Register Bits Description R8: TLB Operations register [31:0] Performs TLB maintenance operations. These are either invalidating all the (unpreserved) entries in the TLB, or invalidating a specific entry. R10: TLB Lockdown register [28:26] and 0 Enables specific page table entries to be locked into the TLB. Locking entries in the TLB guarantees that accesses to the locked page or section can proceed without incurring the time penalty of a TLB miss.
Memory Management Unit (MMU) The translation process always begins in the same way — with a level-one fetch. A section-mapped access requires only a level-one fetch, but a page-mapped access requires an additional level-two fetch. Translation table base The hardware translation process is initiated when the TLB does not contain a translation for the requested MVA.
Working with the CPU Figure 25 shows the table walk process.
Memory Management Unit (MMU) First-level fetch Bits [31:14] of the TTB register are concatenated with bits [31:20] of the MVA to produce a 30-bit address. Figure 26 shows the concatenation and address: Modified virtual address 31 20 19 0 Table index Translation table base 31 14 13 0 Translation base 31 21 0 14 13 Translation base Table index 31 00 0 First-level descriptor Figure 26: Accessing translation table first-level descriptors This address selects a 4-byte translation table entry.
Working with the CPU Fine page tables, which have 1024 entries and split the 1 MB that the table describes into 1 KB blocks. 31 20 19 12 11 10 9 Coarse page table base address Section base address AP Fine page table base address 8 5 4 Domain 1 Domain 1 Domain 1 3 C 2 B 1 0 0 0 Fault 0 1 Coarse page table 1 0 Section 1 1 Fine page table Figure 27: First-level descriptor Table 32 shows first-level descriptor bit assignments.
Memory Management Unit (MMU) Bits Section Coarse Fine Description [1:0] [1:0] [1:0] These bits indicate the page size and validity, and are interpreted as shown in Table 33, “Interpreting first-level descriptor bits [1:0],” on page 86. Table 32: Priority encoding of fault status Value Meaning Description 00 Invalid Generates a section translation fault. 01 Coarse page table Indicates that this is a coarse page table descriptor. 10 Section Indicates that this is a section descriptor.
Working with the CPU Bits Description [8:5] Specifies one of the 16 possible domains (held in the Domain and Access Control register) that contain the primary access controls. 4 Should be written as 1, for backwards compatibility. [3:2] Indicate if the area of memory mapped by this section is treated as writeback cachable, write-through cachable, noncached buffered, or noncached nonbuffered. [1:0] Must be 10 to indicate a section descriptor.
Memory Management Unit (MMU) Bits Description [1:0] Must be 01 to indicate a coarse page descriptor. Table 35: Coarse page table descriptor bits Fine page table descriptor A fine page table descriptor provides the base address of a page table that contains second-level descriptors for large page, small page, or tiny page accesses. Fine page tables have 1024 entries, splitting the 1 MB that the table describes into 1 KB blocks. Figure 30 shows the format of a fine page table descriptor.
Working with the CPU Translating section references Figure 31 shows the complete section translation sequence.
Memory Management Unit (MMU) 31 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Fault Large page base address AP3 AP2 AP1 AP0 C B 0 1 Large page Small page base address AP3 AP2 AP1 AP0 C B 1 0 Small page AP C B 1 1 Tiny page Tiny page base address Figure 32: Second-level descriptor A second-level descriptor defines a tiny, small, or large page descriptor, or is invalid: A large page descriptor provides the base address of a 64 KB block of memory.
Working with the CPU Bits Large Small Tiny Description [11:4] [11:4] [5:4] Access permission bits. See "Domain access control" on page 98 and "Fault checking sequence" on page 99 for information about interpreting the access permission bits. [3:2] [3:2] [3:2] Indicate whether the area of memory mapped by this page is treated as write-back cachable, write-through cachable, noncached buffered, and noncached nonbuffered.
Memory Management Unit (MMU) Modified virtual address 31 1615 20 19 Table index table index 12 11 0 Page index Translation table base 31 14 13 0 14 13 2 1 0 Translation base 31 Translation base Table index 0 0 First-level descriptor 31 10 9 8 54 3 2 1 0 Domain 1 Coarse page table base address 31 10 9 2 1 0 L2 table index Coarse page table base address 0 1 0 0 Second-level descriptor 31 1615 12 1110 9 8 7 6 5 4 3 2 1 0 Page base address AP3 AP2 AP1 AP0 C B 0 1 Physical address
Working with the CPU If the large page descriptor is included in a fine page table, the high-order six bits of the page index and low-order six bits of the fine page table overlap. Each fine page table entry for a large page must be duplicated 64 times.
Memory Management Unit (MMU) If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap. Each fine page table entry for a small page must be duplicated four times.
Working with the CPU Page translation involves one additional step beyond that of a section translation. The first-level descriptor is the fine page table descriptor; this points to the firstlevel descriptor. Note: The domain specified in the first-level description and access permissions specified in the first-level description together determine whether the access has permissions to proceed. See "Domain access control" on page 98 for more information.
Memory Management Unit (MMU) The access control mechanisms of the MMU detect the conditions that produce these faults. If a fault is detected as a result of a memory access, the MMU aborts the access and signals the fault condition to the CPU core. The MMU retains status and address information about faults generated by the data accesses in the Data Fault Status register and Fault Address register (see "Fault Address and Fault Status registers" on page 96).
Working with the CPU Notes: Alignment faults can write either 0b0001 or 0b0011 into Fault Status register [3:0]. Invalid values can occur in the status bit encoding for domain faults. This happens when the fault is raised before a valid domain field has been read from a page table description. Aborts masked by a higher priority abort can be regenerated by fixing the cause of the higher priority abort, and repeating the access. Alignment faults are not possible for instruction fetches.
Memory Management Unit (MMU) Compatibility issues To enable code to be ported easily to future architectures, it is recommended that no reliance is made on external abort behavior. The Instruction Fault Status register is intended for debugging purposes only. Domain access control MMU accesses are controlled primarily through the use of domains. There are 16 domains, and each has a two-bit field to define access to it. Client users and Manager users are supported.
Working with the CPU AP S R Privileged permissions User permissions 00 1 0 Read only Read only 00 0 1 Read only Read only 00 1 1 UNPREDICTABLE UNPREDICTABLE 01 x x Read/write No access 10 x x Read/write Read only 11 x x Read/write Read/write Table 42: Interpreting access permission (AP) bits Fault checking sequence The sequence the MMU uses to check for access faults is different for sections and pages. Figure 36 shows the sequence for both types of access. www.
Memory Management Unit (MMU) Modified virtual address Check address alignment Section translation fault Invalid Section No access (00) Reserved (10) Alignment fault Invalid Page translation fault No access (00) Reserved (10) Page domain fault Violation Page permission fault Get first-level descriptor Page Get page table entry Section domain fault Misaligned Check domain status Section Page Client (01) Client (01) Manager (11) Section permission fault Violation Check access permission
Working with the CPU Alignment faults If alignment fault checking is enabled (the A bit in the R1: Control register is set; see "R1: Control register," beginning on page 58), the MMU generates an alignment fault on any data word access if the address is not word-aligned, or on any halfword access if the address is not halfword-aligned — irrespective of whether the MMU is enabled. An alignment fault is not generated on any instruction fetch or byte access.
Memory Management Unit (MMU) Permission faults If the two-bit domain field returns client (01), access permissions are checked as follows: Section: If the level one descriptor defines a section-mapped access, the AP bits of the descriptor define whether the access is allowed, per Table 42: "Interpreting access permission (AP) bits" on page 98. The interpretation depends on the setting of the S and R bits (see "R1: Control register," beginning on page 58).
Working with the CPU Nonbuffered writes Noncached read-lock-write (SWP) sequence For a read-lock-write (SWP) sequence, the write is always attempted if the read externally aborts. A swap to an NCB region is forced to have precisely the same behavior as a swap to an NCNB region. This means that the write part of a swap to an NCB region can be aborted externally.
Memory Management Unit (MMU) Disabling the MMU Clear bit 0 (the M bit) in the R1: Control register to disable the MMU. Note: If the MMU is enabled, then disabled, then subsequently re-enabled, the contents of the TLB are preserved. If these are now invalid, the TLB must be invalidated before re-enabling the MMU (see "R8:TLB Operations register" on page 68). TLB structure The MMU runs a single unified TLB used for both data accesses and instruction fetches.
Working with the CPU times. To guarantee coherency if a level one descriptor is modified in main memory, either an invalidate-TLB or Invalidate-TLB-by-entry operation must be used to remove any cached copies of the level one descriptor. This is required regardless of the type of level one descriptor (section, level two page reference, or fault). If any of the subpage permissions for a given page are different, each of the subpages are treated separately.
Caches and write buffer The DCache stores the Physical Address Tag (PA tag) corresponding to each DCache entry in the tag RAM for use during cache line write-backs, in addition to the virtual address tag stored in the tag RAM. This means that the MMU is not involved in DCache write-back operations, which removes the possibility of TLB misses to the write-back address.
Working with the CPU Enabling the caches On reset, the ICache and DCache entries all are invalidated and the caches disabled. The caches are not accessed for reads or writes. The caches are enabled using the I, C, and M bits from the R1: Control register, and can be enabled independently of one another. Table 43 gives the I and M bit settings for the ICache, and the associated behavior. R1 I bit R1 M bit ARM926EJ-S behavior 0 ----- ICache disabled.
Caches and write buffer R1 C bit R1 M bit ARM926EJ-S behavior 1 0 DCache enabled, MMU disabled. All data accesses are noncachable, nonbufferable, with no protection checks. All addresses are flat-mapped; that is, VA=MVA=PA. 1 1 DCache enabled, MMU enabled. All data accesses are cachable or noncachable, depending on the page descriptor C bit and B bit (see Table 46: "Page table C and B bit settings for DCache"), and protection checks are performed.
Working with the CPU Cache MVA and Set/Way formats This section shows how the MVA and set/way formats of ARM926EJ-S caches map to a generic virtually indexed, virtually addressed cache. Figure 37 shows a generic, virtually indexed, virtually addressed cache. Tag Index 0 1 2 3 4 5 6 7 Word Byte 0 TAG n 0 1 Hit 2 1 m 2 m m m 3 Read data Figure 37: Generic virtually indexed, virtually addressed cache www.digiembedded.
Caches and write buffer Figure 38 shows the ARM926EJ-S cache format. S+5 S+4 31 5 4 Index Tag 0 1 2 3 4 5 6 7 Word TAG n 0 Figure 38: ARM926EJ-S cache associativity The following points apply to the ARM926EJ-S cache associativity: The group of tags of the same index defines a set. The number of tags in a set is the associativity. The ARM926EJ-S caches are 4-way associative. The range of tags addressed by the index defines a way. The number of tags is a way is the number of sets, NSETS.
Working with the CPU ARM926EJ-S S NSETS 32 KB 8 256 64 KB 9 512 128 KB 10 1024 Table 47: Values of S and NSETS Figure 39 shows the set/way/word format for ARM926EJ-S caches.
Noncachable instruction fetches Self-modifying code A four-word buffer holds speculatively fetched instructions. Only sequential instructions are fetched speculatively; if the ARM926EJ-S issues a nonsequential instruction fetch, the contents of the buffer are discarded (flushed).
Working with the CPU Instruction Memory Barrier Whenever code is treated as data — for example, self-modifying code or loading code into memory — a sequence of instructions called an instruction memory barrier (IMB) operation must be used to ensure consistency between the data and instruction streams processed by the ARM926EJ-S processor.
Instruction Memory Barrier recommended that either a nonbuffered store (STR) or a noncached load (LDR) be used to trigger external synchronization. 4 Invalidate the cache. The ICache must be invalidated to remove any stale copies of instructions that are no longer valid. If the ICache is not being used, or the modified regions are not in cachable areas of memory, this step might not be required. 5 Flush the prefetch buffer.
Memory Controller C H A P T E R 4 T he Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC) peripheral that connects to the Advanced High-performance Bus (AHB). The remainder of this chapter refers to this controller as the memory controller.
Features Features The memory controller provides these features: AMBA 32-bit AHB compliancy. Dynamic memory interface support including SDRAM and JEDEC low-power SDRAM. Asynchronous static memory device support including RAM, ROM, and Flash, with and without asynchronous page mode. Can operate with cached processors with copyback caches. Can operate with uncached processors. Low transaction latency. Read and write buffers to reduce latency and improve performance, particularly for uncached processors.
Memory Controller Support for all AHB burst types. Little and big endian support. Synchronous static memory devices (synchronous burst mode) are not supported. Note: System overview Figure 40 shows the NS9750 memory controller in a sample system.
Features Low-power operation In many systems, the contents of the memory system have to be maintained during low-power sleep modes. NS9750 provides two features to enable this: Dynamic memory refresh over soft reset A mechanism to place the dynamic memories into self-refresh mode Self-refresh mode can be entered as follows: 1 Set the SREFREQ bit in the Dynamic Memory Control register (see page 208). 2 Poll the SREFACK bit in the Status register (see page 207).
Memory Controller Chip select 1 memory configuration You can configure the memory width and chip select polarity of static memory chip select 1 by using selected input signals. This allows you to boot from chip select 1.
Features 8 More boot, initialization, or application code is executed. Example: Boot from flash, SDRAM remapped after boot The system is set up as: Chip select 1 is connected to the boot flash device. Chip select 4 is connected to the SDRAM to be remapped to 0x00000000 after boot. The boot sequence is as follows: 1 120 At power-on, the reset chip select 1 is mirrored into chip select 4 (and chip select 0).
Memory Controller Static memory controller Table 48 shows configurations for the static memory controller with different types of memory devices. See "Static Memory Configuration 0–3 registers" on page 230 for more information.
Static memory controller Write protection Each static memory chip select can be configured for write-protection. SRAM usually is unprotected and ROM devices must be write-protected (to avoid potential bus conflict when performing a write access to ROM), but the P field in the Static Memory Configuration register (see "Static Memory Configuration 0–3 registers" on page 230) can be set to write-protect SRAM as well as ROM devices.
Memory Controller Memory mapped peripherals Some systems use external peripherals that can be accessed using the static memory interface. Because of the way many of these peripherals function, the read and write transfers to them must not be buffered. The buffer must therefore be disabled.
Static memory controller "Static Memory Page Mode Read Delay 0–3 registers" on page 237 (StaticWaitPage[n]) "Static Memory Turn Round Delay 0–3 registers" on page 239 (StaticWaitTurn[n]) "Static Memory Extended Wait register" on page 224 (StaticExtendedWait) The number of cycles in which an AMBA transfer completes is controlled by two additional factors: Access width External memory width Each bank of the memory controller has a programmable enable for the extended wait (EW).
Memory Controller ROM, SRAM, and Flash The memory controller uses the same read timing control for ROM, SRAM, and flash devices. Each read starts with the assertion of the appropriate memory bank chip select signals (STCSOUT_n) and memory address (ADDROUT[27:0]). The read access time is determined by the number of wait states programmed for the WAITRD field in the Static Memory Read Delay register.
Static memory controller Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory address, chip select, and control signals submitted to static memory. T5-T6 Read data returned from the static memory. Data is provided to AHB. Table 50: External memory 0 wait state read Figure 42 shows an external memory read transfer with two wait states (WAITRD=2).
Memory Controller Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory address, chip select, and control signals submitted to static memory. T5-T6 Read wait state 1. T6-T7 Read wait state 2. T7-T8 Read data returned from the static memory. Data is provided to the AHB.
Static memory controller Timing parameter Value WAITRD 2 WAITOEN 2 WAITPAGE N/A WAITWR N/A WAITWEN N/A WAITTURN N/A Table 53: Static memory timing parameters Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory address, chip select, and control signals submitted to static memory. Static memory output enable inactive. T5-T6 Static memory output enable inactive.
Memory Controller Table 55 provides the timing parameters. Table 56 describes the transactions for Figure 44. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 clk_out ADDR A DATAIN 0 D(A) B D(B) STCSOUT_n COEOUT_n Figure 44: External memory 2 0 wait state read timing diagram Timing parameter Value WAITRD 0 WAITOEN 0 WAITPAGE N/A WAITWR N/A WAITWEN N/A WAITTURN N/A Table 55: Static memory timing parameters Cycle Description T0 AHB address provided to memory controller.
Static memory controller Cycle Description T7 AHB address provided to memory controller. T7-T8 AHB transaction processing. T8-T11 Arbitration of AHB memory ports. T11-T12 Static memory address, chip select, and control signals submitted to static memory. T12-T13 Read data returned from static memory. Data is provided to the AHB. Table 56: External memory 2 0wait state reads Figure 45 shows a burst of zero wait state reads with the length specified.
Memory Controller Timing parameter Value WAITWEN N/A WAITTURN N/A Table 57: SRAM timing parameters Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory read 0 address, chip select, and control signals submitted to static memory. T5-T6 Static memory read 1 address, chip select, and control signals submitted to static memory. Read data 0 returned from static memory.
Static memory controller T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 clk_out ADDR A DATAIN A+4 A+8 D(A) D(A+4) SCTSOUT_n COEOUT_n Figure 46: External memory 2 wait states fixed length burst read timing diagram Timing parameter Value WAITRD 2 WAITOEN 0 WAITPAGE N/A WAITWR N/A WAITWEN N/A WAITTURN N/A Table 59: SRAM timing diagrams Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of memory ports.
Memory Controller Cycle Description T7-T8 Read data 0 returned from the static memory. Read data 0 is provided to the AHB. Static memory transfer 1, address, chip select, and control signals submitted to static memory. T8-T9 Read wait state 1. T9-T10 Read wait state 2. T10-T11 Read data 1 returned from the static memory. Read data 1 is provided to the AHB. Static memory transfer 2, address, chip select, and control signals submitted to static memory. T11-T12 Read wait state 1.
Static memory controller T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 clk_out ADDR A DATAIN A+4 D(A) D(A+4) SCTSOUT_n OEOUT_n Figure 47: External memory page mode read transfer timing diagram Timing parameter Value WAITRD 2 WAITOEN 0 WAITPAGE 1 WAITWR N/A WAITWEN N/A WAITTURN N/A Table 61: Static memory timing parameters Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports.
Memory Controller Cycle Description T8-T9 Read page mode wait state 1. T9-T10 Read data 1 returned from the static memory. Read data 1 is provided to the AHB. Static memory transfer 2, address, chip select, and control signals submitted to static memory. T10-T11 Read page mode wait state 1. T11-T12 Read data 2 returned from the static memory. Read data 2 is provided to the AHB. Static memory transfer 3, address, chip select, and control signals submitted to static memory.
Static memory controller Timing parameters Value WAITWR N/A WAITWEN N/A WAITTURN N/A Table 63: Static memory timing parameters Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory transfer m0, address, chip select, and control signals submitted to static memory. T5-T6 Static memory transfer 1, address, chip select, and control signals submitted to static memory.
Memory Controller deasserted a cycle before the chip select, at the end of the transfer. BLSOUT_n (byte lane signal) has the same timing as WEOUT_n (write enable signal) for writes to 8-bit devices that use the byte lane selects instead of the write enables. SRAM Write timing for SRAM starts with assertion of the appropriate memory bank chip selects (STCSOUT[n]_n) and address signals (ADDROUT[27:0]_n).
Static memory controller Timing parameters Value WAITWEN 0 WAITTURN N/A Table 65: Static memory timing parameters Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory transfer 0, address, chip select, and control signals submitted to static memory. Write data is read from the AHB memory port. Write enable inactive. T5-T6 Write enable taken active. Write data submitted to static memory.
Memory Controller T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 clk_out ADDR A DATAOUT D(A) STCSOUT_n WEOUT_n Figure 50: External memory 2 wait state write timing diagram Timing parameter Value WAITRD N/A WAITOEN N/A WAITPAGE N/A WAITWR 2 WAITWEN 0 WAITTURN N/A Table 67: Static memory timing parameters Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports.
Static memory controller Cycle Description T6-T7 Wait state 1. T7-T8 Wait state 2. T8-T9 Static memory writes the data. Write enable taken inactive. T9-T10 Static memory control signals taken inactive. Table 68: External memory 2 wait state write Figure 51 shows a single external memory write transfer with two write enable delay states (WAITWEN=2). One wait state is added. Table 69 provides the timing parameters.
Memory Controller Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports. T4-T5 Static memory transfer 0, address, chip select, and control signals submitted to static memory. Write data is read from the AHB memory port. Write enable active. T5-T6 Write data submitted to static memory. Write enable wait state 1. T6-T7 Write enable wait state 2. T7-T8 Write enable taken active.
Static memory controller T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 clk_out ADDR DATAOUT A 0 D(A) 0 SCTSOUT_n WEOUT_n Figure 52: External memory 2 0 wait writes timing diagram Timing parameter Value WAITRD N/A WAITOEN N/A WAITPAGE N/A WAITWR 0 WAITWEN 0 WAITTURN 0 Table 71: Static memory timing parameters Cycle Description T0 AHB address provided to memory controller. T0-T1 AHB transaction processing. T1-T4 Arbitration of AHB memory ports.
Memory Controller Cycle Description T6-T7 Static memory writes data 0. Write enable taken inactive. Write data 1 is read from AHB memory port. T7-T8 Static memory control signals taken inactive. T8-T9 Memory controller processing. T9-T10 Static memory transfer 1, address, chip select, and control signals submitted to static memory. Write enable inactive. Write data submitted to static memory. T10-T11 Write enable taken active. T11-T12 Static memory writes data 1. Write enable taken inactive.
Static memory controller T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 clk_out ADDR A DATAIN 0 D(A) DATAOUT D(B) OEOUT STCSOUT_n WEOUT_n DATAEN_n Figure 53: Read followed by write (both 0 wait) with no turnaround Timing parameter Value WAITRD 0 WAITOEN 0 WAITPAGE N/A WAITWR 0 WAITWEN 0 WAITTURN 0 Table 73: Static memory timing parameters Cycle Description T0 AHB address provided to the memory controller. T0-T1 AHB transaction processing.
Memory Controller Cycle Description T5-T6 Memory controller processing. T6-T7 Memory controller processing. T7-T8 Static memory transfer address, chip select, and control signals submitted to static memory. Write data is read from AHB memory port. Write enable inactive. T8-T9 Write enable taken active. Write data submitted to static memory. T9-T10 Static memory control signals taken inactive. T10-T11 Memory controller processing.
Static memory controller Table 75 provides the timing parameters. Table 76 describes the transactions for Figure 54.
Memory Controller Cycle Description T4-T5 Static memory address, chip select, and control signals submitted to static memory. Write data is read from AHB memory port. Write enable inactive. AHB read address provided to memory controller. T5-T6 Write enable taken active. Write data submitted to static memory. T6-T7 Static memory writes the data. Write enable taken inactive. T7-T8 Static memory control signals taken inactive.
Static memory controller Table 77 provides the timing parameters. Table 78 describes the transactions for Figure 55.
Memory Controller Cycle Description T4-T5 Static memory address, chip select, and control signals submitted to static memory. T5-T6 Read data returned from static memory. Data is provided to the AHB. AHB write address provided to memory controller. T6-T7 Turn around cycle 1. T7-T8 Turn around cycle 2. T8-T9 Static memory transfer address, chip select, and control signals submitted to static memory. Write enable inactive. T9-T10 Memory controller processing. T10-T11 Write enable taken active.
Static memory controller partitioned memory devices" on page 150 and "Memory banks constructed from 8-bit or non-byte-partitioned memory devices" on page 150 explain why different connections, with respect to WEOUT_n and BLSOUT[3:0]_n, for different memory configurations. Address connectivity The static memory address output signal ADDROUT[27:0] must be right-justified.
Memory Controller Figure 56: Memory banks constructed from 8-bit memory Figure 56 shows 8-bit memory configuring memory banks that are 8-, 16-, and 32-bits wide. In each of these configurations, the BLSOUT[3:0]_n signals are connected to write enable (WE_n) inputs of each 8-bit memory. The WEOUT signal from the memory controller is not used. For write transfers, the appropriate BLSOUT[3:0]_n byte lane signals are asserted low, and direct the data to the addressed bytes.
Static memory controller ADDROUT[20:0] A[20:0] STCSOUT_n CE_n OEOUT_n OE_n WEOUT_n WE_n BLSOUT[3]_n B[3]_n BLSOUT[2]_n B[2]_n BLSOUT[1]_n B[1]_n BLSOUT[0]_n DATA[31:0] B[0]_n IO[31:0] 32-bit bank consisting of one 32-bit device Figure 58: Memory banks constructed from 32-bit memory Figure 59 shows connections for a typical memory system with different data width memory devices.
Memory Controller ADDROUT[20:0] ADDROUT[20:0] DATAOUT[31:0] A[20:0] STCSOUT[0]_n Q[31:0] DATA OUT[31:0] CE_n OEOUT_n OE_n 2Mx32 burst mask ROM ADDROUT[15:0] DATAOUT[31:16] A[15:0] STCSOUT[1]_n IO[15:0] CE_n OE_n WEOUT_n WE_n UB_n LB_n ADDROUT[15:0] DATAOUT[15:0] A[15:0] IO[15:0] CE_n OE_n WE_n UB_n LB_n 64Kx16 SRAM, two off ADDROUT[16:0] DATAOUT[31:24] A[16:0] STCSOUT[2]_n IO[7:0] CE_n OE_n BLSOUT[3]_n WE_n ADDROUT[16:0] DATAOUT[23:16] A[16:0] IO[7:0] CE_n OE_n BLSOUT[2]_n WE_n AD
Static memory controller Byte lane control and databus steering For little and big endian configurations, address right-justified The tables in this section (Table 79 through Table 125) show the relationship of signals HSIZE[2:0], HADDR[1:0], ADDROUT[1:0], and BLSOUT[3:0] and mapping of data between the AHB system databus and the external memory databus. This mapping applies to both the static and dynamic memory controllers.
Memory Controller Access: Read, little endian, 16-bit external bus External data mapping on to system databus Internal transfer width HRDATA to DATA HSIZE [2:0] HADDR [1:0] ADDROUT [0] BLSOU T [1:0] [31:24] 23:16] [15:8] [7:0] Word (2 transfers 010 -- 1 0 00 00 [15:8] - [7:0] - [15:8] [7:0] Halfword 001 1- 1 00 [15:8] [7:0] - - Halfword 001 0- 0 00 - - [15:8] [7:0] Byte 000 11 1 01 [15:8] - - - Byte 000 10 1 10 - [7:0] - - Byte 000 01 0 01 - -
Static memory controller Access: Read, little endian, 32-bit external bus External data mapping on to system databus Internal transfer width HRDATA to DATA HSIZE [2:0] HADDR [1:0] BLSOUT [3:0] [31:24] [23:16] [15:8] [7:0] Byte 000 10 1011 - [23:16] - - Byte 000 01 1101 - - [15:8] - Byte 000 00 1110 - - - [7:0] Table 81: Little endian read, 32-bit external bus Access: Write, little endian, 8-bit external bus Internal transfer width DATA to HRDATA HSIZE [2:0] HADD R [1:0]
Memory Controller Access: Write, little endian, 16-bit external bus System data mapping on to external databus Internal transfer width DATA to HRDATA HSIZE [2:0] HADD R [1:0] ADDROUT [0] BLSOU T [1:0] [31:24] [23:16] [15:8] [7:0] Word (2 transfers 010 -- 1 0 00 00 -- - [31:24] [15:8] [23:16] [7:0] Halfword 001 1- 1 00 - - [31:24] [23:16] Halfword 001 0- 0 00 - - [15:8] [7:0] Byte 000 11 1 01 - - [31:24] - Byte 000 10 1 10 - - - [23:16] Byte 000 01
Static memory controller Access: Write, little endian, 32-bit external bus System data mapping on to external databus Internal transfer width DATA to HRDATA HSIZE [2:0] HADDR [1:0] BLSOUT [3:0] [31:24] [23:16] [15:8] [7:0] Byte 000 01 1101 - - [15:8] - Byte 000 00 1110 - - - [7:0] Table 84: Little endian write, 32-bit external bus Access: Read, big endian, 8-bit external bus External data mapping on to system databus Internal transfer width HRDATA to DATA HSIZE [2:0] HADDR [1
Memory Controller Access: Read, big endian, 16-bit external bus External data mapping on to system databus Internal transfer width HRDATA to DATA HSIZE [2:0] HADDR [1:0] ADDROUT [1:0] BLSOU T [1:0] [31:24] 23:16] [15:8] [7:0] Word (2 transfers 010 -- 10- 00 00 [15:8] [7:0] [15:8] - [7:0] - Halfword 001 1- 1- 00 - - [15:8] [7:0] Halfword 001 0- 0- 00 [15:8] [7:0] - - Byte 000 11 1- 10 - - - [7:0] Byte 000 10 1- 01 - - [15:8] - Byte 000 01 0- 10 -
Static memory controller Access: Read, big endian, 32-bit external bus External data mapping on to system databus Internal transfer width HRDATA to DATA HSIZE [2:0] HADDR [2:1] ADDROUT [1:0] BLSOU T [3:0] [31:24] 23:16] [15:8] [7:0] Byte 000 01 -- 1011 - [23:16] - - Byte 000 00 -- 0111 [31:24] - - - Table 87: Big endian read, 32-bit external bus Access: Write, big endian, 8-bit external bus Internal transfer width DATA to HRDATA HSIZE [2:0] HADD R [1:0] ADDROUT [1:0] BLSOU
Memory Controller Access: Write, big endian, 16-bit external bus System data mapping on to external databus Internal transfer width DATA to HRDATA HSIZE [2:0] HADD R [1:0] ADDROUT [1:0] BLSOU T [1:0] [31:24] [23:16] [15:8] [7:0] Word (2 transfers 010 -- 10- 00 00 -- - [15:8][3 1:24] [7:0] [23:16] Halfword 001 1- 1- 00 - - [15:8] [7:0] Halfword 001 0- 0- 00 - - [31:24] [23:16] Byte 000 11 1- 10 - - - [7:0] Byte 000 10 1- 01 - - [15:8] - Byte 000 01
Dynamic memory controller Access: Write, big endian, 32-bit external bus System data mapping on to external databus Internal transfer width DATA HSIZE [2:0] HADDR [1:0] BLSOUT [3:0] [31:24] [23:16] [15:8] [7:0] Byte 000 01 1011 - [23:16] - - Byte 000 00 0111 [31:24] - - - Table 90: Big endian write, 32-bit external bus Dynamic memory controller Write protection Each dynamic memory chip select can be configured for write-protection by setting the appropriate bit in the write prote
Memory Controller Word transfers are the widest transfers supported by the memory controller. Any access tried with a size larger than a word generates an error response. Address mapping This section provides tables that show how AHB address bus addresses map to the external dynamic memory address ADDROUT[14:0] for different memory configurations and bus widths.
Dynamic memory controller devices. The row-bank-column address mapping scheme allows memory accesses to be performed efficiently to nearby memory regions. – 32-bit wide databus address mappings (BRC) (see "32-bit wide databus address mappings (BRC)" on page 175). These address mappings are used for 32-bit data bus chip select with SDR-SDRAM or low power SDR-SDRAM. The bank-row-column address mapping scheme allows the low-power SDRSDRAM memory features to be used efficiently.
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 8 8 19 - 7 7 18 9 6 6 17 8 5 5 16 7 4 4 15 6 3 3 14 5 2 2 13 4 1 1 12 3 0 0 11 2 Table 91: Address mapping for 16M SDRAM (1Mx16, RBC) Table 92 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 14 used as bank select).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 3 3 15 5 2 2 14 4 1 1 13 3 0 0 12 2 Table 92: Address mapping for 16M SDRAM (2Mx8, RBC) Table 93 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (2Mx32, pins 13 and 14 used as bank selects).
Memory Controller Table 94 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects).
Dynamic memory controller Table 95 shows the outputs from the memory controller and the corresponding inputs to the 64 M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 11 11 23 - 10 10/AP 22 AP 9 9 21 - 8 8 20 - 7 7 19 9 6 6 18 8 5 5 17 7 4 4 16 6 3 3 15 5 2 2 14 4 1 1 13 3 0 0 12 2 Table 96: Address mapping for 128M SDRAM (4Mx32, RBC) Table 97 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx16, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 6 6 19 8 5 5 18 7 4 4 17 6 3 3 16 5 2 2 15 4 1 1 14 3 0 0 13 2 Table 97: Address mapping for 128 SDRAM (8Mx16, RBC) Table 98 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (16Mx8, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 1 1 15 3 0 0 14 2 Table 98: Address mapping for 128 SDRAM (16Mx8, RBC) Table 99 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (8Mx32, pins 13 and 14 used as bank selects).
Dynamic memory controller Table 100 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 11 11 25 - 10 10/AP 24 AP 9 9 23 11 8 8 22 10 7 7 21 9 6 6 20 8 5 5 19 7 4 4 18 6 3 3 17 5 2 2 16 4 1 1 15 3 0 0 14 2 Table 101: Address mapping for 256M SDRAM (32Mx8, RBC) Table 102 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 6 6 20 8 5 5 19 7 4 4 18 6 3 3 17 5 2 2 16 4 1 1 15 3 0 0 14 2 Table 102: Address mapping for 512M SDRAM (32Mx16, RBC) Table 103 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 1 1 16 3 0 0 15 2 Table 103: Address mapping for 512M SDRAM (64Mx8, RBC) 32-bit wide databus address mappings (BRC) Table 104 through Table 116 show 32-bit wide databus address mappings for several SDRAM (BRC) devices. Table 104 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (1x16, pin 14 used as bank select).
Dynamic memory controller Table 105 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 13 used as bank select).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 11 - - - 10 10/AP 20 AP 9 9 19 - 8 8 18 - 7 7 17 9 6 6 16 8 5 5 15 7 4 4 14 6 3 3 13 5 2 2 12 4 1 1 11 3 0 0 10 2 Table 106: Address mapping for 64M SDRAM (2Mx32, BRC) Table 107 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 6 6 16 8 5 5 15 7 4 4 14 6 3 3 13 5 2 2 12 4 1 1 11 3 0 0 10 2 Table 107: Address mapping for 64M SDRAM (4Mx16, BRC) Table 108 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 1 1 12 3 0 0 11 2 Table 108: Address mapping for 64M SDRAM (8Mx8, BRC) Table 109 shows the outputs from the memory controller and the corresponding inputs to the 128M SDSRAM (4Mx32, pins 13 and 14 used as bank selects).
Dynamic memory controller Table 110 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (8Mx16, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 11 11 23 - 10 10/AP 22 AP 9 9 21 11 8 8 20 10 7 7 19 9 6 6 18 8 5 5 17 7 4 4 16 6 3 3 15 5 2 2 14 4 1 1 13 3 0 0 12 2 Table 111: Address mapping for 128M SDRAM (16Mx8, BRC) Table 112 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (8Mx32, pins 13 and 14 used as bank selects.
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 6 6 16 8 5 5 15 7 4 4 14 6 3 3 13 5 2 2 12 4 1 1 11 3 0 0 10 2 Table 112: Address mapping for 256M SDRAM (8Mx32, BRC) Table 113 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 1 1 12 3 0 0 11 2 Table 113: Address mapping for 256M SDRAM (16Mx16, BRC) Table 114 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects).
Dynamic memory controller Table 115 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 11 11 24 12 10 10/AP 23 AP 9 9 22 11 8 8 21 10 7 7 20 9 6 6 19 8 5 5 18 7 4 4 17 6 3 3 16 5 2 2 15 4 1 1 14 3 0 0 13 2 Table 116: Address mapping for 512M SDRAM (64x8, BRC) 16-bit wide databus address mappings, SDRAM (RBC) Table 117 through Table 126 show 16-bit wide databus address mappings for SDRAM (RBC) devices.
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 9 9 19 - 8 8 18 - 7 7 17 8 6 6 16 7 5 5 15 6 4 4 14 5 3 3 13 4 2 2 12 3 0 0 10 ** Table 117: Address mapping for 16M SDRAM (1Mx16, RBC) Table 118 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 13 used as bank select).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 4 4 16 5 3 3 15 4 2 2 14 3 1 1 13 2 0 0 12 ** Table 118: Address mapping for 16M SDRAM (2Mx8, RBC) Table 119 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects).
Dynamic memory controller Table 120 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx8, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 11 11 23 - 10 10/AP 22 AP 9 9 21 - 8 8 20 9 7 7 19 8 6 6 18 7 5 5 17 6 4 4 16 5 3 3 15 4 2 2 14 3 1 1 13 2 0 0 12 ** Table 121: Address mapping for 128M SDRAM (8Mx16, RBC) Table 122 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (16Mx8, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 6 6 19 7 5 5 18 6 4 4 17 5 3 3 16 4 2 2 15 3 1 1 14 2 0 0 13 ** Table 122: Address mapping for 128M SDRAM (16Mx8, RBC) Table 123 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 1 1 13 2 0 0 12 ** Table 123: Address mapping for 256M SDRAM (16Mx16, RBC) Table 124 shows the outputs from the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects).
Dynamic memory controller Table 125 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects).
Memory Controller Table 126 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 14 - - - 13 BA 20 20 12 - - - 11 - - - 10 10/AP 19 AP 9 9 18 - 8 8 17 - 7 7 16 8 6 6 15 7 5 5 14 6 4 4 13 5 3 3 12 4 2 2 11 3 1 1 10 2 0 0 9 ** Table 127: Address mapping for 16M SDRAM (1Mx16, BRC) Table 128 shows the outputs from the memory controller and the corresponding inputs to the 16M SDRAM (2Mx8, pin 1
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 9 9 19 - 8 8 18 9 7 7 17 8 6 6 16 7 5 5 15 6 4 4 14 5 3 3 13 4 2 2 12 3 1 1 11 2 0 0 10 ** Table 128: Address mapping for 16M SDRAM (2Mx8, BRC) Table 129 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (4Mx16, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 4 4 13 5 3 3 12 4 2 2 11 3 1 1 10 2 0 0 9 ** Table 129: Address mapping for 64M SDRAM (4Mx16, BRC) Table 130 shows the outputs from the memory controller and the corresponding inputs to the 64M SDRAM (8Mx*, pins 13 and 14 used as bank selects).
Memory Controller Table 131 shows the outputs from the memory controller and the corresponding inputs to the 128M SDRAM (8Mx16, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 11 11 22 - 10 10/AP 21 AP 9 9 20 10 8 8 19 9 7 7 18 8 6 6 17 7 5 5 16 6 4 4 15 5 3 3 14 4 2 2 13 3 1 1 12 2 0 0 11 ** Table 132: Address mapping for 128M SDRAM (16Mx8, BRC) Table 133 shows the outputs for the memory controller and the corresponding inputs to the 256M SDRAM (16Mx16, pins 13 and 14 used as bank selects).
Memory Controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 6 6 16 7 5 5 15 6 4 4 14 5 3 3 13 4 2 2 12 3 1 1 11 2 0 0 10 ** Table 133: Address mapping for 256M SDRAM (16Mx16, BRC) Table 134 shows the outputs for the memory controller and the corresponding inputs to the 256M SDRAM (32Mx8, pins 13 and 14 used as bank selects).
Dynamic memory controller Output address ( ADDROUT) Memory device connections AHB address to row address AHB address to column address 1 1 12 2 0 0 11 ** Table 134: Address mapping for 256M SDRAM (32Mx8, BRC) Table 135 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (32Mx16, pins 13 and 14 used as bank selects).
Memory Controller Table 136 shows the outputs from the memory controller and the corresponding inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects).
Registers Registers The external memory is accessed using the AHB memory interface ports. Addresses are not fixed, but are determined by the AHB decoder and can be different for any particular system implementation. Transfers to the external memory controller memories are selected by the HSELMPMC[3:0]CS[7:0] signals (where [3:0] indicates the AHB port number and [7:0] indicates the chip select to be accessed.) Register map Table 137 lists the registers in the Memory Controller register map.
Memory Controller Address Register Description A070 0048 DynamictRC Dynamic Memory Active to Active Command Period (tRC) A070 004C DynamictRFC Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) A070 0050 DynamictXSR Dynamic Memory Exit Self-Refresh to Active Command (tXSR) A070 0054 DynamictRRD Dynamic Memory Active Bank A to Active B Time (tRRD) A070 0058 DynamictMRD Dynamic Memory Load Mode register to Active Command Time (tMRD) A070 0080 StaticExtende
Registers Address Register Description A070 022C StaticWaitRd1 Static Memory Read Delay 1 A070 0230 StaticWaitPage1 Static Memory Page Mode Read Delay 1 A070 0234 StaticWaitWr1 Static Memory Write Delay 1 A070 0238 StaticWaitTurn1 Static Memory Turn Round Delay 1 A070 0240 StaticConfig2 Static Memory Configuration Register 2 A070 0244 StaticWaitWen2 Static Memory Write Enable Delay 2 A070 0248 StaticWaitOen2 Static Memory Output Enable Delay 2 A070 024C StaticWaitRd2 Static Memory
Memory Controller Control register Address: A070 0000 The Control register controls the memory controller operation. The control bits can be changed during normal operation.
Registers Bits Access Mnemonic Description D01 R/W ADDM Address mirror 0 Normal memory map 1 Reset memory map. Static memory chip select 1 is mirrored onto chip select 0 and chip select 4 (reset value on reset_n) Indicates normal or reset memory map. On power-on reset, chip select 1 is mirrored to both chip select 0 and chip select 1/chip select 4 memory areas. Clearing the M bit allows chip select 0 and chip select 4 memory to be accessed.
Memory Controller Status register Address: A070 0004 The Status register provides memory controller status information.
Registers The Configuration register configures memory controller operation. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Memory Controller The Dynamic Memory Control register controls dynamic memory operation. The control bits can be changed during normal operation.
Registers Bits Access Mnemonic Description D02 R/W SR Self-refresh request (SREFREQ) 0 Normal mode 1 Enter self-refresh mode (reset value on reset_n) By writing 1 to this bit, self-refresh can be entered under software control. Writing 0 to this bit returns the memory controller to normal mode. The self-refresh acknowledge bit in the Status register (see page 207) must be polled to discover the current operating mode of the memory controller.
Memory Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved REFRESH Register bit assignment Bits Access Mnemonic Description D31:11 N/A Reserved N/A (do not modify) D10:0 R/W REFRESH Refresh timer 0x0 Refresh disabled (reset value on reset_n) 0x1–0x77F n(x16) 16n HCLK ticks between SDRAM refresh cycles Table 142: Dynamic Memory Refresh Timer register Examples Generic formula: DynamicRefresh = (((t
Registers Dynamic Memory Read Configuration register Address: A070 0028 The Dynamic Memory Read Configuration register allows you to configure the dynamic memory read strategy. Modify this register only during system initialization. The Dynamic Memory Read Configuration register is used for all four dynamic memory chip selects. The worst case value for all chip selects must be programmed.
Memory Controller Dynamic Memory Precharge Command Period register Address: A070 0030 The Dynamic Memory Precharge Command Period register allows you to program the precharge command period, tRP. Modify this register only during system initialization. This value normally is found in SDRAM datasheets as tRP. The Dynamic Memory Precharge Command Period register is used for all four dynamic memory chip selects. The worst case value for all chip selects must be programmed.
Registers Dynamic Memory Active to Precharge Command Period register Address: A070 0034 The Dynamic Memory Active to Precharge Command Period register allows you to program the active to precharge command period, tRAS. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter lowpower or disabled mode. This value normally is found in SDRAM datasheets as tRAS.
Memory Controller Dynamic Memory Self-refresh Exit Time register Address: A070 0038 The Dynamic Memory Self-refresh Exit Time register allows you to program the selfrefresh exit time, tSREX. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. This value normally is found in SDRAM data sheets as tSREX.
Registers Dynamic Memory Last Data Out to Active Time register Address: A070 003C The Dynamic Memory Last Data Out to Active Time register allows you to program the last-data-out to active command time, tAPR. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. This value normally is found in SDRAM datasheets as tAPR.
Memory Controller Dynamic Memory Data-in to Active Command Time register Address: A070 0040 The Dynamic Memory Data-in to Active Command Time register allows you to program the data-in to active command time, tDAL. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. This value normally is found in SDRAM data sheets as tDAL or tAPW.
Registers Dynamic Memory Write Recovery Time register Address: A070 0044 The Dynamic Memory Write Recovery Time register allows you to program the write recovery time, tWR. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. This value normally is found in SDRAM datasheets as tWR, tDPL, tRWL, or tRDL.
Memory Controller Dynamic Memory Active to Active Command Period register Address: A070 0048 The Dynamic Memory Active to Active Command Period register allows you to program the active to active command period, tRC. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter lowpower or disabled mode. This value normally is found in SDRAM datasheets as tRC.
Registers Dynamic Memory Auto Refresh Period register Address: A070 004C The Dynamic Memory Auto Refresh Period register allows you to program the autorefresh period and the auto-refresh to active command period, tRFC. It is recommended that this register be modified during initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. This value normally is found in SDRAM datasheets as tRFC or tRC.
Memory Controller Dynamic Memory Exit Self-refresh register Address: A070 0050 The Dynamic memory Exit Self-refresh register allows you to program the exit selfrefresh to active command time, tXSR. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode. This value normally is found in SDRAM datasheets as tXSR.
Registers Dynamic Memory Active Bank A to Active Bank B Time register Address: A070 0054 The Dynamic Memory Active Bank A to Active Bank B Time register allows you to program the active bank A to active bank B latency, tRRD. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter lowpower or disabled mode. This value normally is found in SDRAM datasheets as tRRD.
Memory Controller Dynamic Memory Load Mode register to Active Command Time register Address: A070 0058 The Dynamic Memory Load Mode register to Active Command Time register allows you to program the Load Mode register to active command time, tMRD. It is recommended that this register be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Registers Static Memory Extended Wait register Address: A070 0080 The Static Memory Extended Wait register times long static memory read and write transfers (which are longer than can be supported by the Static Memory Read Delay registers (see page 236) or the Static Memory Write Delay registers (see page 238)) when the EW (extended wait) bit in the related Static Memory Configuration register (see page 230) is enabled.
Memory Controller Example Static memory read/write time = 16 us CLK frequency = 50 MHz This value must be programmed into the Static Memory Extended Wait register: (16 x 10-6 x 50 x 106 / 16) - 1 = 49 Dynamic Memory Configuration 0–3 registers Address: A070 0100 / 0120 / 0140 / 0160 The Dynamic Memory Configuration 0–3 registers allow you to program the configuration information for the relevant dynamic memory chip select. These registers are usually modified only during system initialization.
Registers Bits Access Mnemonic Description D14 R/W AM Address mapping 0 Reset value on reset_n See Table 157, “Address mapping,” on page 226 for more information. D13 N/A Reserved N/A (do not modify) D12:07 R/W AM1 Address mapping 00000000 Reset value on reset_n The SDRAM column and row width and number of banks are computed automatically from the address mapping. See Table 157, “Address mapping,” on page 226 for more information.
Memory Controller [14] [12] [11:9] [8:7] Description 0 0 011 00 256 Mb (32Mx8), 4 banks, row length=13, column length=10 0 0 011 01 256 Mb (16Mx16), 4 banks, row length=13, column length=9 0 0 100 00 512 Mb (64Mx8), 4 banks, row length=13, column length=11 0 0 100 01 512 Mb (32Mx16), 4 banks, row length=13, column length=10 16-bit external bus low-power SDRAM address mapping (bank, row, column) 0 1 000 00 16 Mb (2Mx8), 2 banks, row length=11, column length=9 0 1 000 01 16
Registers [14] [12] [11:9] [8:7] Description 1 0 100 00 512 Mb (64Mx8), 4 banks, row length=13, column length=11 1 0 100 01 512 Mb (32Mx16), 4 banks, row length=13, column length=10 32-bit extended bus low-power SDRAM address mapping (bank, row, column) 1 1 000 00 16 Mb (2Mx8), 2 banks, row length=11, column length=9 1 1 000 01 16 Mb (1Mx16), 2 banks, row length=11, column length=8 1 1 001 00 64 Mb (8Mx8), 4 banks, row length=12, column length=9 1 1 001 01 64 MB (4Mx16), 4
Memory Controller Dynamic Memory RAS and CAS Delay 0–3 registers Address: A070 0104 / 0124 / 0144 / 0164 The Dynamic Memory RAS and CAS Delay 0–3 registers allow you to program the RAS and CAS latencies for the relevant dynamic memory. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter lowpower or disabled mode.
Registers Static Memory Configuration 0–3 registers Address: A070 0200 / 0220 / 0240 / 0260 The Static Memory Configuration 0–3 registers configure the static memory configuration. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Memory Controller Bits Access Mnemonic Description D08 R/W EW Extended wait 0 Extended wait disabled (reset value on reset_n) Extended wait enabled Extended wait uses the Static Extended Wait register (see page 224) to time both the read and write transfers, rather than the Static Memory Read Delay 0–3 registers (see page 236) and Static Memory Write Delay 0–3 registers (see page 238). This allows much longer transactions.
Registers Bits Access Mnemonic Description D07 R/W PB Byte lane state 0 For reads, all bits in byte_lane_sel_n[3:0] are high. 1 For writes, the respective active bits in byte_lane_sel_n[3:0] are low (reset value for chip select 0, 2, and 3 on reset_n). For reads, the respective active bits in byte_lane_sel_n[3:0] are low. For writes, the respective active bits in byte_lane_sel_n[3:0] are low. Note: Setting this bit to 0 disables the write enable signal.
Memory Controller Bits Access Mnemonic Description D03 R/W PM Page mode 0 Disabled (reset on reset_n) 1 Async page mode enabled (page length four) In page mode, the memory controller can burst up to four external accesses. Devices with asynchronous page mode burst four or higher are supported. Asynchronous page mode burst two devices are not supported and must be accessed normally.
Registers Static Memory Write Enable Delay 0–3 registers Address: A070 0204 / 0224 / 0244 / 0264 The Static Memory Write Enable Delay 0–3 registers allow you to program the delay from the chip select to the write enable assertion. The Static Memory Write Enable Delay register is used in conjunction with the Static Memory Write Delay registers, to control the width of the write enable signals.
Memory Controller Static Memory Output Enable Delay 0–3 registers Address: A070 0208 / 0228 / 0248 / 0268 The Static Memory Output Enable Delay 0–3 registers allow you to program the delay from the chip select or address change, whichever is later, to the output enable assertion. The Static Memory Output Enable Delay register is used in conjunction with the Static Memory Read Delay registers, to control the width of the output enable signals.
Registers Static Memory Read Delay 0–3 registers Address: A070 020C / 022C / 024C / 026C The Static Memory Read Delay 0–3 registers allow you to program the delay from the chip select to the read access. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Memory Controller Static Memory Page Mode Read Delay 0–3 registers Address: A070 0210 / 0230 / 0250 / 0270 The Static Memory Page Mode Read Delay 0–3 registers allow you to program the delay for asynchronous page mode sequential accesses. These registers control the overall period for the read cycle. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions.
Registers Static Memory Write Delay 0–3 registers Address: A070 0214 / 0234 / 0254 / 0274 The Static Memory Write Delay 0–3 registers allow you to program the delay from the chip select to the write access. These registers control the overall period for the write cycle. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Memory Controller Static Memory Turn Round Delay 0–3 registers Address: A070 0218 / 0238 / 0258 / 0278 The Static Memory Turn Round Delay 0–3 registers allow you to program the number of bus turnaround cycles. It is recommended that these registers be modified during system initialization, or when there are no current or outstanding transactions. Wait until the memory controller is idle, then enter low-power or disabled mode.
Registers 240 NS9750 Hardware Reference
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Registers 242 NS9750 Hardware Reference
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Registers 244 NS9750 Hardware Reference
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Registers 246 NS9750 Hardware Reference
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Registers 248 NS9750 Hardware Reference
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Registers 250 NS9750 Hardware Reference
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System Control Module C H A P T E R 5 T he System Control Module configures and oversees system operations for the NS9750, and defines both the NS9750 AHB arbiter system and system memory address space.
System Control Module features System Control Module features The System Control Module uses the following to configure and maintain NS9750 system operations: AHB arbiter system System-level address decoding 18 programmable timers – Watchdog timer – Bus monitor timer for the system bus (a second bus monitor timer, for peripheral devices, is discussed in the BBus Bridge chapter) – 16 general purpose timers/counters Interrupt controller Multiple configuration and status registers System Sleep/Wake-up
System Control Module met. See "Arbiter configuration examples" on page 258 for information about configuring the AHB arbiter. The NS9750 high-speed bus system is split into two subsystems: High-speed peripheral subsystem: Connects all high-speed peripheral devices to a port on the external memory controller. CPU subsystem: Connects the CPU directly to a second port on the external memory controller. Figure 60 shows an overview of the NS9750 high-speed bus architecture.
System bus arbiter Main arbiter. Contains a 16-entry Bus Request Configuration (BRC) register. Each BRC entry represents a bus request and grant channel. Each request/ grant channel can be assigned to only one bus master at a time. Each bus master can be connected to multiple request/grant channels simultaneously, however, depending on the bus bandwidth requirement of that master.
System Control Module Ownership Ownership of the data bus is delayed from ownership of the address/control bus. When hready indicates that a transfer is complete, the master that owns the address/ control bus can use the data bus — and continues to own that data bus — until the transaction completes. Note: If a master is assigned more than one request/grant channel, these channels need to be set and reset simultaneously to guarantee that a nonrequesting master will not occupy the system bus.
System bus arbiter SPLIT transfers A SPLIT transfer occurs when a slave is not ready to perform the transfer. The slave splits, or masks, its master, taking away the master’s bus ownership and allowing other masters to perform transactions until the slave has the appropriate resources to perform its master’s transaction. The bus arbiter supports SPLIT transfers.
System Control Module Example 1 Since the 20 Mbyte per master guarantee meets the requirements of all masters, the AHB arbiter will be programmed as follows: BRC0[31:24] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S BRC0[23:16] = 8’b1_0_00_0001 channel enabled, 100%, Ethernet Rx BRC0[15:8] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S BRC0[7:0] = 8’b1_0_00_0010 channel enabled, 100% Ethernet Tx BRC1[31:24] = 8’b1_0_00_0000 channel enabled, 100%, ARM926EJ-S BRC1[23:16] = 8’b1_0_00_
System bus arbiter The available bandwidth per master is calculated using this formula: Bandwidth per master: = [(100MHz/2) / (16 clock cycles per access x 6 masters)] x 32 bytes = 16.667 Mbytes/master If the LCD is configured for two arbiter channel slots, then, there are 33.334 Mbytes available, which is greater than the 25 Mbytes required. Each of the other masters have 16.667 Mbytes available, which is more than enough to meet their requirements.
System Control Module Address decoding A central address decoder provides a select signal — hsel_x — for each slave on the bus. Table 166 shows how the system memory address is set up to allow access to the internal and external resources on the system bus. Note that the external memory chip select ranges can be reset after powerup.
Address decoding Address range Size System functions 0xA010 0000 – 0xA01F FFFF 1 MB PCI CONFIG_ADDR 0xA020 0000 – 0xA02F FFFF 1 MB PCI CONFIG_DATA 0xA030 0000 – 0xA03F FFFF 1 MB PCI arbiter 0xA040 0000 – 0xA04F FFFF 1 MB BBUS-to-AHB bridge 0xA050 0000 – 0xA05F FFFF 1 MB Reserved 0xA060 0000 – 0xA06F FFFF 1 MB Ethernet Communication Module 0xA070 0000 – 0xA07F FFFF 1 MB Memory controller 0xA080 0000 – 0xA08F FFFF 1 MB LCD controller 0xA090 0000 – 0xA09F FFFF 1 MB System Control
System Control Module Programmable timers NS9750 provides 18 programmable timers: Software watchdog timer Bus monitor timer 16 general purpose timers Software watchdog timer The software watchdog timer, set to specific time intervals, handles gross system misbehaviors. The watchdog timer can be set to timeout in longer ranges of time intervals, typically in seconds. The software watchdog timer can be enabled or disabled, depending on the operating condition.
Programmable timers in the appropriate Timer Control register (see "Timer 0–15 Control registers" on page 301). With a 16-bit counter and a 16-bit prescaler, each GPTC can measure external event length up to minutes in range, and can be individually enabled or disabled. GPTCs can be configured to reload, with the value defined in the appropriate Timer Reload Count register (see page 284), and generates an interrupt upon terminal count.
System Control Module // This command file initializes the debugger local variables that are // used by the user defined On-Stop and Idle-Mode command descriptors. // // NOTE: DO NOT CHANGE THIS FILE. This file configures the resources // needed to use this feature.
Programmable timers // Examples: // // ew MAJIC_ON_STOP_CMD = 1, @$ucd_rd8, FFF00003 // // Defines an On-Stop command that reads the byte at 0xFFF00003 upon // stopping. // // ew MAJIC_ON_STOP_CMD = 1, @$ucd_rmw16, 80000000, C00, F00 // // Defines an On-Stop command that reads a 16-bit value from 80000000, // masks off bits 11..8, sets those bits to 1100, and writes the result // back to 80000000.
System Control Module Interrupt controller The interrupt system is a simple two-tier priority scheme. Two lines access the CPU core and can interrupt the processor: IRQ (normal interrupt) and FIQ (fast interrupt). FIQ has a higher priority than IRQ. FIQ interrupts Most sources of interrupts on NS9750 are from the IRQ line. There is only one FIQ source for timing-critical applications.
Interrupt controller Interrupt Source 0 Interrupt Source 1 Priority Level 0 (highest) Interrupt Source 31 IRQ Invert Interrupt Source ID Reg 0 FIQ Enable Winning Priority Level Interrupt Source 0 Interrupt Source 1 Priority Level 1 Interrupt Source 31 Active Interrupt Level Reg Interrupt Vector Address Reg Level 0 Invert Interrupt Source ID Reg 1 Priority Encoder Interrupt Vector Address Reg Level 1 ISADDR Reg Enable Interrupt Vector Address Reg Level 31 Interrupt Source 0 Interrupt Source 1
System Control Module The NS9750 interrupt sources are assigned as shown: Interrupt ID Interrupt source 0 Watchdog Timer 1 AHB Bus Error 2 BBus Aggregate Interrupt 3 Reserved 4 Ethernet Module Receive Interrupt 5 Ethernet Module Transmit Interrupt 6 Ethernet Phy Interrupt 7 LCD Module interrupt 8 PCI Bridge Module Interrupt 9 PCI Arbiter Module Interrupt 10 PCI External Interrupt 0 11 PCI External Interrupt 1 12 PCI External Interrupt 2 13 PCI External Interrupt 3 14 I2C Inte
Interrupt controller Interrupt ID Interrupt source 26 Timer Interrupt 12 and 13 27 Timer Interrupt 14 and 15 28 External Interrupt 0 29 External Interrupt 1 30 External Interrupt 2 31 External Interrupt 3 Vectored interrupt controller (VIC) flow A vectored interrupt controller allows a reasonable interrupt latency for IRQ-line interrupts. When an interrupt occurs, the CPU processor determines whether the interrupt is from a FIQ or IRQ line.
System Control Module System attributes System software can configure these NS9750 system attributes: Little endian/big endian mode Watchdog timer enable Watchdog timeout generates IRQ/FIQ/RESET Watchdog timeout interval Enable/disable ERROR response for misaligned data access System module clock enables Enable access to internal registers in USER mode Bus monitor enable Bus monitor timeout interval Bus arbiter timer enable Bus arbiter timeout period Bus arbiter timeout response (IRQ/FIQ/RESET) Bus bandwid
System attributes Figure 62 shows how the PLL clock is used to provide the NS9750 system clocks. 29.4912 MHz PLL CN x1_sys_osc OSC 20MHz 40MHz x2_sys_osc FN MUL by ND (27) DIV by FS (2) BP Note, to use an external oscillator, place a 100 ohm resistor in series between the oscillator and x1 set by strapping FBM div by 2 fixed cpu_clock (199.0656 MHz) div by 4 fixed ahb_clock (99.5328 MHz) div by 8 fixed bbus_clock (49.
System Control Module Table 168 indicates how each bit is used to configure the powerup settings, where 1 indicates the internal pullup resistor and 0 indicates an external pulldown resistor. Table 169 shows PLL ND[4:0] multiplier values.
System attributes Pin name Configuration bits reset_done Bootup mode 0 Boot from SDRAM using serial SPI EEPROM 1 Boot from flash/ROM gpio[19] PLL BP (PLL bypass) 0 PLL bypassed 1 PLL not bypassed gpio[17], gpio[12], gpio[10], gpio[8], gpio[4] PLL ND[4:0] (PLL multiplier, ND+1) See Table 169: "PLL ND[4:0] multiplier values.
System Control Module Register configuration: gpio 17, 12, 10, 8, 4 Multiplier 10001 21 10110 20 10111 19 10100 18 10101 17 01010 16 01011 15 01000 14 01001 13 01110 12 01111 11 01100 10 01101 9 00010 8 00011 7 00000 6 00001 5 00110 4 00111 3 00100 2 00101 1 Table 169: PLL ND[4:0] multiplier values www.digiembedded.
System configuration registers There are 32 additional GPIO pins that are used to create a general purpose, userdefined ID register (see "Gen ID register" on page 311). These external signals are registered at powerup.
System Control Module Offset [31:24] [23:16] A090 0048 Timer 1 Reload Count register A090 004C Timer 2 Reload Count register A090 0050 Timer 3 Reload Count register A090 0054 Timer 4 Reload Count register A090 0058 Timer 5 Reload Count register A090 005C Timer 6 Reload Count register A090 0060 Timer 7 Reload Count register A090 0064 Timer 8 Reload Count register A090 0068 Timer 9 Reload Count register A090 006C Timer 10 Reload Count register A090 0070 Timer 11 Reload Count register
System configuration registers Offset [31:24] [23:16] A090 00B4 Timer 12 Read register A090 00B8 Timer 13 Read register A090 00BC Timer 14 Read register A090 00C0 Timer 15 Read register A090 00C4 Interrupt Vector Address Register Level 0 A090 00C8 Interrupt Vector Address Register Level 1 A090 00CC Interrupt Vector Address Register Level 2 A090 00D0 Interrupt Vector Address Register Level 3 A090 00D4 Interrupt Vector Address Register Level 4 A090 00D8 Interrupt Vector Address Register
System Control Module Offset [31:24] [23:16] [15:8] [7:0] A090 0120 Interrupt Vector Address Register Level 23 A090 0124 Interrupt Vector Address Register Level 24 A090 0128 Interrupt Vector Address Register Level 25 A090 012C Interrupt Vector Address Register Level 26 A090 0130 Interrupt Vector Address Register Level 27 A090 0134 Interrupt Vector Address Register Level 28 A090 0138 Interrupt Vector Address Register Level 29 A090 013C Interrupt Vector Address Register Level 30 A090 014
System configuration registers Offset [31:24] [23:16] A090 018C Active Interrupt Level register A090 0190 Timer 0 Control register A090 0194 Timer 1 Control register A090 0198 Timer 2 Control register A090 019C Timer 3 Control register A090 01A0 Timer 4 Control register A090 01A4 Timer 5 Control register A090 01A8 Timer 6 Control register A090 01AC Timer 7 Control register A090 01B0 Timer 8 Control register A090 01B4 Timer 9 Control register A090 01B8 Timer 10 Control register A0
System Control Module Offset [31:24] [23:16] [15:8] A090 01F8 System Memory Chip Select 1 Static Memory Base A090 01FC System Memory Chip Select 1 Static Memory Mask A090 0200 System Memory Chip Select 2 Static Memory Base A090 0204 System Memory Chip Select 2 Static Memory Mask A090 0208 System Memory Chip Select 3 Static Memory Base A090 020C System Memory Chip Select 3 Static Memory Mask A090 0210 GenID— General purpose, user-defined ID register A090 0214 External Interrupt 0 Control
System configuration registers AHB Arbiter Gen Configuration register Address: A090 0000 The AHB Arbiter Gen Configuration register contains miscellaneous control settings for the AHB bus arbiter.
System Control Module BRC0, BRC1, BRC2, and BRC3 registers Address: A090 0004 / 0008 / 000C / 0010 The BRC[0:3] registers control the AHB arbiter bandwidth allocation scheme. Table 172 shows how the channels are assigned in the four registers. Table 173 shows the bit definition, or format, for each channel, using data bits [07:00] as the example.
System configuration registers Bits Access Mnemonic Reset Description D05:04 R/W BRF 0x0 Bandwidth reduction field 00 100% 01 75% 10 50% 11 25% Programs the weight for each AHB bus master. Used to limit the round robin scheduler. D03:00 R/W HMSTR 0x0 hmaster Program a particular AHB bus master number here. Note that a particular master can be programmed to more than one channel.
System Control Module Timer 0–15 Read register Address: A090 0084 / 0088 / 008C / 0090 / 0094 / 0098 / 009C / 00A0 / 00A4 / 00A8 / 00AC / 00B0 / 00B4 / 00B8 / 00BC / 00C0 The Timer Read registers read the current state of each Timer register.
System configuration registers Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W IVARV 0x0 Interrupt Vector Address register value Provides the interrupt vector address for the specified interrupt level.
System Control Module 31 30 29 28 27 26 25 24 23 22 Int Config registers 0, 4, 8, 12, 16, 20, 24, 28 15 14 13 12 11 10 21 20 19 18 17 16 1 0 Int Config registers 1, 5, 9, 13, 17, 21, 25, 29 9 Int Config registers 2, 6, 10, 14, 18, 22, 26, 30 8 7 6 5 4 3 2 Int Config registers 3, 7, 11, 15, 19, 23, 27, 31 IE INV IT Interrupt source ID Register bit assignment BIts Access Mnemonic Reset Definition D07 R/W IE 0x0 Interrupt enable 0 Interrupt is disabled 1 Interrupt
System configuration registers ISRADDR register Address: A090 0164 The ISRADDR register provides the current ISRADDR value. The Interrupt Vector Address register for the FIQ interrupt must be assigned a unique value. If this unique address is seen by the IRQ service routine, software must read the ISRADDR register again. The correct IRQ interrupt service routine address is read the second time.
System Control Module Interrupt Status Active Address: A090 0168 The Interrupt Status Active register shows the current interrupt request.
System configuration registers Interrupt Status Raw Address: A090 016C The Interrupt Status Raw register shows all current interrupt requests.
System Control Module Timer Interrupt Status register Address: A090 0170 The Timer Interrupt Status register shows all current timer interrupt requests.
System configuration registers Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07 R/W SWWE 0x0 Software watchdog enable 0 Software watchdog disabled 1 Software watchdog enabled. Once this is set, it cannot be cleared. D06 N/A Reserved N/A N/A D05 R/W SWWI 0x0 Software watchdog interrupt clear Write a 1, then a 0 to this bit to clear the software watchdog interrupt.
System Control Module Software Watchdog Timer register Address: A090 0178 The Software Watchdog Timer register services the watchdog timer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Watchdog timer 15 14 13 12 11 10 9 8 7 Watchdog timer Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W WT 0x0 Watchdog timer A read to this register gives the current value of the watchdog timer, but will not change the contents.
System configuration registers Register bit assignment Bits Access Mnemonic Reset Description D31:10 N/A Reserved N/A N/A D09:07 R/W LPCS 0x0 LCD panel clock select 000 AHB clock 001 AHB clock / 2 010 AHB clock / 4 011 AHB clock / 8 1xx LCD clock provided by external clock D06 R/W BBC 0x1 BBus 0 Clock disabled 1 Clock enabled D05 R/W LCC 0x1 LCD controller 0 Clock disabled 1 Clock enabled D04 R/W MCC 0x1 Memory controller 0 Clock disabled 1 Clock enabled D03 R/W PARBC 0x1
System Control Module Reset and Sleep Control register Address: A090 0180 The Reset and Sleep Control register resets each module on the AHB bus. To use sleep mode, the CPU must reset and stop the clocks to all modules not used to wake up the CPU. The memory controller must be reset and then re-enabled. The code that resets the memory controller must be loaded into instruction cache first. The last step is to set the CSE bit (D19) in the Reset and Sleep Control register.
System configuration registers Bits Access Mnemonic Reset Definition D18 R/W SMWE 0x0 Serial character match wake-up enable 0 Do not wake up on receipt of a character match by the serial module. 1 Wake up on receipt of a character match by the serial module. D17 R/W EWE 0x0 Ethernet wake-up enable 0 Do not wake up on receipt of an Ethernet packet. 1 Wake up on receipt of an Ethernet packet. D16 R/W PI3WE 0x0 PCI interrupt 3 wake-up enable 0 Do not wake up on PCI interrupt 3 input signal.
System Control Module The Miscellaneous System Configuration and Status register configures miscellaneous system configuration bits.
System configuration registers Bits Access Mnemonic Reset Description D09:08 R CS1DW HW strap boot_strap[ 4], boot_strap[ 3] Chip select 1 data width HW strap setting 00 8 bits 01 16 bits 10 32 bits 11 Reserved Status bits indicating the hardware strap setting of external memory chip select 1 data width. The data width can be changed by writing to the appropriate control register in the memory controller.
System Control Module Bits Access Mnemonic Reset Description D00 R/W IRAM0 0x0 Internal register access mode bit 0 0 Allow access to internal registers using PRIVILEGED mode only 1 Allow access to internal registers using PRIVILEGED or USER mode. Table 187: Miscellaneous System Configuration and Status register PLL Configuration register Address: A090 0188 The PLL Configuration register configures the PLL.
System configuration registers Bits Access Mnemonic Reset Description D20:16 R PLLND HW strap gpio[17], gpio[12], gpio[10], gpio[8], gpio[4] PLL ND status[4:0] Status register to determine the powerup strapping settings or the new settings as changed by software. D15 W PLLSW 0x0 PLL SW change Write a 1 to this bit to change the PLL settings as defined in bits D09:00. Note: The system is held in reset until the PLL is locked and settled.
System Control Module Active Interrupt Level Status register Address: A090 018C The Active Interrupt Level Status register shows the current active interrupt level. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved INTID Register bit assignment Bits Access Mnemonic Reset Description D31:06 N/A Reserved N/A N/A D05:00 R INTID 0x0 Interrupt The level of the current active interrupt.
System configuration registers Register bit assignment Bits Access Mnemonic Reset Description 31:16 N/A Reserved N/A N/A D15 R/W TEN 0x0 Timer enable 0 Timer is disabled 1 Timer is enabled D14:10 N/A Reserved N/A N/A D09 R/W INTC 0x0 Interrupt clear Clears the timer interrupt. System software must write a 1, then a 0 to this location to clear the interrupt.
System Control Module Bits Access Mnemonic Reset Description D05:04 R/W TM 0x0 Timer mode 00 Internal timer or external event 01 External low-level, gated timer 10 External high-level, gated timer 11 Concatenate the lower timer. Not applicable on timer 0. Note: When either external gated timer option is selected, the timer clock select bits (08:06) determine the frequency.
System configuration registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 0 base (CS0B) 15 14 13 12 11 10 9 8 7 Chip select 0 base (CS0B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 0 mask (CS0M) 15 14 13 12 11 10 9 8 7 Chip select 0 mask (CS0M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS0B 0x00000 Chip select 0 base B
System Control Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 1 base (CS1B) 15 14 13 12 11 10 9 8 7 Chip select 1 base (CS1B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 1 mask (CS1M) 15 14 13 12 11 10 9 8 7 Chip select 1 mask (CS1M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS1B 0x10000 Chip select 1 base Base addre
System configuration registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 2 base (CS2B) 15 14 13 12 11 10 9 8 7 Chip select 2 base (CS2B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 2 mask (CS2M) 15 14 13 12 11 10 9 8 7 Chip select 2 mask (CS2M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS2B 0x20000 Chip select 2 base B
System Control Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 3 base (CS3B) 15 14 13 12 11 10 9 8 7 Chip select 3 base (CS3B) 31 30 29 6 Reserved 28 27 26 25 24 23 22 Chip select 3 mask (CS3M) 15 14 13 12 11 10 9 8 7 Chip select 3 mask (CS3M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS3B 0x30000 Chip select 3 base Base addre
System configuration registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 0 base (CS0B) 15 14 13 12 11 10 9 8 7 Chip select 0 base (CS0B) 31 30 29 28 6 Reserved 27 26 25 24 23 22 Chip select 0 mask (CS0M) 15 14 13 12 11 10 9 8 7 Chip select 0 mask (CS0M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS0B 0x40000 Chip select 0 base B
System Control Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 1 base (CS1B) 15 14 13 12 11 10 9 8 7 Chip select 1 base (CS1B) 31 30 29 28 6 Reserved 27 26 25 24 23 22 Chip select 1 mask (CS1M) 15 14 13 12 11 10 9 8 7 Chip select 1 mask (CS1M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS1B 0x50000 Chip select 1 base Base addre
System configuration registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 2 base (CS2B) 15 14 13 12 11 10 9 8 7 Chip select 2 base (CS2B) 31 30 29 28 6 Reserved 27 26 25 24 23 22 Chip select 2 mask (CS2M) 15 14 13 12 11 10 9 8 7 Chip select 2 mask (CS2M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS2B 0x60000 Chip select 2 base B
System Control Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 21 20 19 18 17 16 5 4 3 2 1 0 Chip select 3 base (CS3B) 15 14 13 12 11 10 9 8 7 Chip select 3 base (CS3B) 31 30 29 28 6 Reserved 27 26 25 24 23 22 Chip select 3 mask (CS3M) 15 14 13 12 11 10 9 8 7 Chip select 3 mask (CS3M) 6 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:12 R/W CS3B 0x70000 Chip select 3 base Base addre
System configuration registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 GENID 15 14 13 12 11 10 9 8 7 GENID Register bit assignment Bits Access Mnemonic Reset Description D31:00 R GENID Reflects the status of the GPIO inputs at reset. The GPIO signals are listed in "Bootstrap initialization," beginning on page 272.
System Control Module External Interrupt 0–3 Control register Address: A090 0214 / 0218 / 021C / 0220 The External Interrupt Control registers control the behavior of external interrupts 0–3. The external interrupts are behind GPIO (see "GPIO MUX," beginning on page 34).
Ethernet Communication Module C H A P T E R 6 T he Ethernet Communication module consists of an Ethernet Media Access Controller (MAC) and Ethernet front-end module. The Ethernet MAC interfaces to an external PHY through one of two industry-standard interfaces: MII and RMII. The Ethernet front-end module provides all of the control functions to the MAC.
Overview Overview The Ethernet MAC module provides the following: Station address logic (SAL) Statistics module Interface to MII (Media Independent Interface) PHY Interface to RMII (Reduced Media Independent Interface) PHY The Ethernet front-end module does the following: Provides control functions to the MAC Buffers and filters the frames received from the MAC Pumps transmit data into the MAC Moves frames between the MAC and the system memory Reports transmit and receive status to the host “Legend” RX_RD
Ethernet Communication Module Ethernet PHY TX RX MGMT Hash Table Host Interface Flow Control Receive Transmit Ethernet MAC Ethernet Front End SYSTEM BUS Figure 63: Ethernet Communication module block diagram Ethernet MAC The Ethernet MAC includes a full function 10/100 Mbps Media Access Controller (MAC), station address filtering logic (SAL), statistic collection module (STAT), and two software-selectable PHY interfaces — MII and RMII.
Ethernet MAC MAC CORE TRANSMIT DATA PHY INTERFACE Tx DATA MCS TFUN TRANSMIT STATUS SYSTEM INTERFACE MODULE RECEIVE DATA ACCEPT/ REJECT Tx CONTROL RMII Rx DATA PHY RECEIVE STATUS CONTROL/ STATUS MII RFUN Rx CONTROL CONTROL/ STATUS HOST CLK & RESET STAT MIIM SAL Figure 64: Ethernet MAC block diagram Feature Description MAC Core 10/100 megabit Media Access Controller Performs the CSMA/CD function.
Ethernet Communication Module Feature Description MIIM MII management Provides control/status path to MII and RMII PHYs. STAT Statistics module Counts and saves Ethernet statistics. SAL Station address logic Performs destination address filtering. MII Media Independent Interface Provides the interface from the MAC core to a PHY that supports the MII (as described in the IEEE 802.3 standard).
Ethernet MAC External IO MII RMII RXD[3] RXD[3] N/C Pull low external to NS9750 RXD[2] RXD[2] N/C Pull low external to NS9750 RXD[1] RXD[1] RXD[1] RXD[0] RXD[0] RXD[0] RX_DV RX_DV N/C Pull low external to NS9750 RX_ER RX_ER RX_ER Optional signal; pull low external to NS9750 if not being used RX_CLK RX_CLK REF_CLK TXD[3] TXD[3] N/C TXD[2] TXD[2] N/C TXD[1] TXD[1] TXD[1] TXD[0] TXD[0] TXD[0] TX_EN TX_EN TX_EN TX_ER TX_ER N/C TX_CLK TX_CLK N/C Pull low external to N
Ethernet Communication Module Station address logic (SAL) The station address logic module examines the destination address field of incoming frames, and filters the frames before they are stored in the Ethernet front-end module. The filtering options, listed next, are programmed in the Station Address Filter register (see page 366).
Ethernet MAC If any of the counters roll over, an associated carry bit is set in the Carry 1 (CAR1) or Carry 2 (CAR2) registers (see "General Statistics registers," beginning on page 377). Any statistics counter overflow can cause the STOVFL bit in the Ethernet Interrupt Status register (see page 385) to be set if its associated mask bit is not set in Carry Mask Register 1 or Carry Mask Register 2 (see "General Statistics registers," beginning on page 377).
Ethernet Communication Module Ethernet front-end module Figure 65 shows the Ethernet front-end module (EFE).
Ethernet front-end module memory. Bad frames (for example, invalid checksum or code violation) and frames with unacceptable destination addresses are discarded. The 2K byte RX_FIFO allows the entire Ethernet frame to be buffered while the receive byte count is analyzed. The receive byte count is analyzed by the receive packet processor to select the optimum-sized buffer for transferring the received frame to system memory. The processor can use one of four different-sized receive buffers in system memory.
Ethernet Communication Module to be received and written into the receive FIFO, but the frame remains in the FIFO until the system wakes up. Normal frame filtering is still performed. When a qualified frame is inserted into the receive FIFO, the receive packet processor notifies the system power controller, which performs the wake up sequence. The frame remains in the receive FIFO until the system wakes up.
Ethernet front-end module used is read from system memory and stored in the registers internal to the RX_RD logic. 31 30 29 28 16 15 OFFSET + 0 Source Address OFFSET + 4 Buffer Length (11 lower bits used) OFFSET + 8 OFFSET + C 0 Destination Address (not used) W I E F Reserved Status Figure 66: Receive buffer descriptor format Field Description W WRAP bit, which, when set, tells the RX_RD logic that this is the last buffer descriptor in the ring.
Ethernet Communication Module Field Description Buffer length This is a dual use field: When the buffer descriptor is read from system memory, buffer length indicates the maximum sized frame, in bytes, that can be stored in this buffer ring. When the RX_RD logic writes the descriptor back from the receive status FIFO into system memory at the end of the frame, the buffer length is the actual frame length, in bytes.
Ethernet front-end module Field Description I When set, tells the TX_WR logic to set TXBUFC in the Ethernet Interrupt Status register (see page 385) when the buffer is closed due to a normal channel completion. Buffer pointer 32-bit pointer to the start of the buffer in system memory. This pointer can be aligned on any byte of a 32-bit word. Status Lower 16 bits of the Ethernet Transmit Status register.
Ethernet Communication Module Setting the EXTDMA (enable transmit DMA) bit in Ethernet General Control Register #1 starts the transfer of transmit frames from the system memory to the TX_FIFO. The TX_WR logic reads the first buffer descriptor in the TX buffer descriptor RAM. If the F bit is set, it transfers data from system memory to the TX_FIFO using the buffer pointer as the starting point. This process continues until the end of the buffer is reached.
Ethernet front-end module contain the correct value. In this situation, software must keep track of the location of the next buffer descriptor to be kicked off. If the TX_WR logic detects that the frame was aborted or had an error, the logic updates the current buffer descriptor as described in the previous paragraph.
Ethernet Communication Module The slave also generates an AHB ERROR if the address is not aligned on a 32-bit boundary, and the misaligned bus address response mode is set in the Miscellaneous System Configuration register (see "Miscellaneous System Configuration and Status register," beginning on page 296). In addition, accesses to non-existent addresses result in an AHB ERROR response. Interrupts Separate RX and TX interrupts are provided back to the system.
Ethernet front-end module Interrupt condition Description Interrupt Transmit buffer not ready F bit not set in transmit buffer descriptor when read from TX buffer descriptor RAM, for a frame in progress. TX Transmit complete Frame transmission complete. TX TXERR Frame not transmitted successfully. TX TXIDLE TX_WR logic in idle mode because there are no frames to send.
Ethernet Communication Module Active state Default state Modules reset MII Management Configuration register 1 0 MAC MIIM logic PHY Support register 1 0 RMII Bit field Register RMIIM RPERMII Table 204: Reset control www.digiembedded.
External CAM filtering External CAM filtering NS9750 supports external Ethernet CAM filtering, which requires an external CAM controller to operate in conjunction with the MAC inside NS9750. The interface to the CAM controller is provided through GPIO in NS9750.
Ethernet Communication Module RX_CLK RXD[3:0] CAM_REQ 5 D 2 1 4 3 6 5 7 8 9 A B C Reject Setup to End of Packet (4 RXCLKs) Preamble/ SFD 5 RXCLKs CAM_REJECT Reject Hold From End of Packet (3 RXCLKs) Figure 68: External Ethernet CAM filtering for MII PHY In this example, the MII receive interface is transferring a frame whose first 6 nibbles have the values 1, 2, 3, 4, 5, and 6. The external CAM hardware uses the CAM_REQ signal to find the alignment for the destination address.
External CAM filtering REF_CLK CRS_DV Note 1 RXD[1:0] 00 00 00 01 01 01 01 01 01 Preamble 11 00 10 11 SFD 01 11 10 11 Packet Data 1. Rising edge of CRS_DV asynchronous relative to REF_CLK 2. CRS_DV synchronous to REF_CLK once RXD[1:0] changes from "00" to "01" at start of preamble.
Ethernet Communication Module Ethernet Control and Status registers Table 205 shows the address for each Ethernet controller register. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
Ethernet Control and Status registers Address Register Description A060 0448 SA3 Station Address register #3 A060 0500 SAFR Station Address Filter register A060 0504 HT1 Hash Table Register #1 A060 0508 HT2 Hash Table Register #2 A060 0680 STAT Statistics Register Base (45 registers) A060 0A00 RXAPTR RX_A Buffer Descriptor Pointer register A060 0A04 RXBPTR RX_B Buffer Descriptor Pointer register A060 0A08 RXCPTR RX_C Buffer Descriptor Pointer register A060 0A0C RXDPTR RX_D Buff
Ethernet Communication Module Ethernet General Control Register #1 Address: A060 0000 31 30 29 28 ERX ERX DMA Rsvd ERX SHT 15 14 13 12 PHY_MODE Rsvd 27 26 25 24 Not used 11 Not used 10 9 RX MAC_ ALIGN HRST 8 23 22 ETX ETX DMA 7 6 21 20 Not used 5 19 18 ERX INIT 4 3 17 16 Reserved 2 1 0 Reserved ITXA Register bit assignment Bits Access Mnemonic Reset Description D31 R/W ERX 0 Enable RX packet processing (see "Receive packet processor" on page 324) 0 Res
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D28 R/W ERXSHT 0 Accept short (<64) receive frames 0 Do not accept short frames 1 Accept short frames When set, allows frames that are smaller than 64 bytes to be accepted by the RX_WR logic. ERXSHT is typically set for debugging only. D27:24 R/W Not used 0 Always write as 0.
Ethernet Communication Module Bits Access Mnemonic Reset Description D19 R/W ERXINIT 0 Enable initialization of RX buffer descriptors 0 Do not initialize 1 Initialize When set, causes the RX_RD logic to initialize the internal buffer descriptor registers for each of the four pools from the buffer descriptors pointed to by RXAPTR, RXBPTR, RXCPTR, and RXDPTR. This is done as part of the RX initialization process.
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D08 R/W ITXA 0 Insert transmit source address 0 Source address for Ethernet transmit frame taken from data in TX_FIFO. 1 Insert the MAC Ethernet source address into the Ethernet transmit frame source address field. Set to force the MAC to automatically insert the Ethernet MAC source address into the Ethernet transmit frame source address. The SA1, SA2, and SA3 registers provide the address information.
Ethernet Communication Module Bits Access Mnemonic Reset Description D03 R/W TCLER 0 Clear transmit error 0->1 transition: Clear transmit error. Clears out conditions in the transmit packet processor that have caused the processor to stop and require assistance from software before the processor can be restarted (for example, an AHB bus error or the TXBUFNR bit set in the Ethernet Interrupt Status register (see page 385)). Toggle this bit from low to high to restart the transmit packet processor.
Ethernet Control and Status registers Ethernet General Status register Address: A060 0008 31 30 29 28 27 26 25 24 23 22 21 Reserved 15 14 13 12 11 10 20 19 RX INIT 9 8 7 6 5 4 18 17 16 Reserved 3 2 1 0 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:21 N/A Reserved N/A N/A D20 R/C RXINIT 0x0 RX initialization complete Set when the RX_RD logic has completed the initialization of the local buffer descriptor registers requested when
Ethernet Communication Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 TX OK TX BR TX MC TX AL TX AED TX AEC TX AUR TX AJ Not used TX DEF TX CRC Not used TXCOLC Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 R TXOK 0x0 Frame transmitted OK When set, indicates that the frame has been delivered to and emptied from the transmit FIFO without problems.
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D10 R TXAEC 0x0 TX abort — excessive collisions When set, indicates that the frame was aborted because the number of collisions exceeded the value set in the Collision Window/Retry register. If this bit is set, the TX_WR logic stops processing frames and sets the TXERR bit in the Ethernet Interrupt Status register.
Ethernet Communication Module Bits Access Mnemonic Reset Description D04 R Not used 0x0 Always set to 0. D03:00 R TXCOLC 0x0 Transmit collision count Number of collisions the frame incurred during transmission attempts. Table 209: Ethernet Transmit Status register Ethernet Receive Status register Address: A060 001C The Ethernet Receive Status register contains the status for the last completed receive frame.
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D15 R RXCE 0x0 Receive carrier event previously seen When set, indicates that a carrier event activity (an activity on the receive channel that does not result in a frame receive attempt being made) was found at some point since the last receive statistics.
Ethernet Communication Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 SRST Not used 13 12 Reserved 11 10 9 8 Not used RPER FUN RPE MCST RPET FUN 7 Reserved LOOP BK Not used RXEN Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 R/W SRST 1 Soft reset Set this bit to 1 to reset the RX_WR, TX_RD, MAC (except host interface), SAL (except host interface), and RMII modules.
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D00 R/W RXEN 0 Receive enable Set this bit to 1 to allow the MAC receiver to receive frames.
Ethernet Communication Module MAC Configuration Register #2 Address: A060 0404 MAC Configuration Register #2 provides additional bits that control functionality within the Ethernet MAC block.
Ethernet Control and Status registers Bits Access Mnemonic Reset Definition D08 R/W PUREP 0 Pure preamble enforcement 0 No preamble checking is performed 1 The MAC certifies the content of the preamble to ensure that it contains 0x55 and is error-free.
Ethernet Communication Module Bits Access Mnemonic Reset Definition D02 R/W HUGE 0 Huge frame enable 0 Transmit and receive frames are limited to the MAXF value in the Maximum Frame register (see "Maximum Frame register" on page 357). 1 Frames of any length are transmitted and received. D01 R/W Not used 0 Always write as 0. D00 R/W FULLD 0 Full-duplex 0 The MAC operates in half-duplex mode. 1 The MAC operates in full-duplex mode.
Ethernet Control and Status registers Back-to-Back Inter-Packet-Gap register Address: A060 0408 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Reserved IPGT Register bit assignment Bits Access Mnemonic Reset Description D31:07 N/A Reserved N/A N/A D06:00 R/W IPGT 0x00 Back-to-back inter-packet-gap Programmable field that indicates the nibble time offset of the minimum period between the end of any transmitted
Ethernet Communication Module Non Back-to-Back Inter-Packet-Gap register Address: A060 040C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 Rsvd 12 11 10 9 IPGR1 8 7 Rsvd IPGR2 Register bit assignment Bits Access Mnemonic Reset Description D31:15 N/A Reserved N/A N/A D14:08 R/W IPGR1 0x00 Non back-to-back inter-packet-gap part 1 Programmable field indicating optional carrierSense window (referenced in IEEE 8.2.3/4.2.3.2.1).
Ethernet Control and Status registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 Reserved 12 11 10 9 8 7 CWIN Reserved RETX Register bit assignment Bits Access Mnemonic Reset Description D31:14 N/A Reserved N/A N/A D13:08 R/W CWIN 0x37 Collision window Programmable field indicating the slot time or collision window during which collisions occur in properly configured networks.
Ethernet Communication Module Maximum Frame register Address: A060 0414 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 MAXF Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15:00 R/W MAXF 0x0600 Maximum frame length Default value of 0x600 represents a maximum receive frame of 1536 octets. An untagged maximum-size Ethernet frame is 1518 octets.
Ethernet Control and Status registers PHY Support register Address: A060 0418 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 RPER MII 12 11 10 9 Not used 8 7 Not used SPEED Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 R/W RPERMII 0 Reset RMII module Set to 1 to reset the RMII PHY interface module logic. D14:09 R/W Not used 0x08 Always write 0x08.
Ethernet Communication Module MII Management Configuration register Address: A060 0420 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 SPRE Not used Reserved 15 14 13 12 11 10 RMIIM 9 8 7 Reserved CLKS Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 R/W RMIIM 0 Reset MII management block Set this bit to 1 to reset the MII Management module.
Ethernet Control and Status registers Clocks field settings AHB bus clock for 2.5 MHz AHB bus clock for 12.
Ethernet Communication Module Bits Access Mnemonic Reset Description D01 R/W SCAN 0 Automatically scan for read data Set to 1 to have the MII Management module perform read cycles continuously. This is useful for monitoring link fail, for example. Note: D00 R/W READ 0 SCAN must transition from a 0 to a 1 to initiate the continuous read cycles. Single scan for read data Set to 1 to have the MII Management module perform a single read cycle.
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D12:08 R/W DADR 0x00 MII PHY device address Represents the 5-bit PHY device address field for management cycles. Up to 32 different PHY devices can be addressed. D07:05 N/A Reserved N/A N/A D04:00 R/W RADR 0x00 MII PHY register address Represents the 5-bit PHY register address field for management cycles. Up to 32 registers within a single PHY device can be addressed.
Ethernet Communication Module MII Management Read Data register Address: A060 0430 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 MRDD Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15:00 R MRDD 0x0000 MII read data Read data is obtained by reading from this register after an MII Management read cycle.
Ethernet Control and Status registers Register bit assignment Bits Access Mnemonic Reset Description D31:04 N/A Reserved N/A N/A D03 R MIILF 0 MII link failure When set to 1, indicates that the PHY currently has a link fail condition. D02 R NVALID 0 Read data not valid When set to 1, indicates that the MII Management read cycle has not completed and the read data is not yet valid. Also indicates that SCAN READ is not valid for automatic scan reads.
Ethernet Communication Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 OCTET4 OCTET3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 OCTET6 OCTET5 Bits Access Mnemonic Reset Description Station Address Register #1 D31:16 N/A Reserved N/A N/A D15:08 R/W OCTET1 0 Station address octet #1 (stad[7:0]) D07:00 R/W OCTET2 0 St
Ethernet Control and Status registers Station Address Filter register Address: A060 0500 The Station Address Filter register contains several filter controls. The register is located in the station address logic (see "Station address logic (SAL)" on page 321). All filtering conditions are independent of each other. For example, the station address logic can be programmed to accept all multicast frames, all broadcast frames, and frames to the programmed destination address.
Ethernet Communication Module HT1 stores enables for the lower 32 CRC addresses; HT2 stores enables for the upper 32 CRC addresses.
Ethernet Control and Status registers Statistics registers Address: A060 0680 (base register) The Statistics module has 39 counters and 4 support registers that count and save Ethernet statistics. The Ethernet General Control Register #2 contains three Statistics module configuration bits: AUTOZ, CLRCNT, and STEN. The counters support a “clear on read” capability that is enabled when AUTOZ is set to 1.
Ethernet Communication Module Receive statistics counters Address Register Receive counters R/W A060_069C RBYT Receive byte counter R/W A060_06A0 RPKT Receive packet counter R/W A060_06A4 RFCS Receive FCS error counter R/W A060_06A8 RMCA Receive multicast packet counter R/W A060_06AC RBCA Receive broadcast packet counter R/W A060_06B0 RXCF Receive control frame packet counter R/W A060_06B4 RXPF Receive PAUSE frame packet counter R/W A060_06B8 RXUO Receive unknown OPCODE co
Ethernet Control and Status registers Receive packet counter (A060 06A0) Incremented for each received frame (including bad packets, and all unicast, broadcast, and multicast packets). D31:18 R Reset = Read as 0 Reserved D17:00 R/W Reset = 0x00000 RPKT Receive FCS error counter (A060 06A4) Incremented for each frame received with a length of 64 to 1518 bytes, and containing a frame check sequence (FCS) error.
Ethernet Communication Module Receive control frame packet counter (A060 06B0) Incremented for each MAC control frame received (PAUSE and unsupported). D31:12 R Reset = Read as 0 Reserved D11:00 R/W Reset = 0x000 RXCF Receive PAUSE frame packet counter (A060 06B4) Incremented each time a valid PAUSE control frame is received.
Ethernet Control and Status registers Receive carrier sense error counter (A060 06C8) Incremented each time a false carrier is found during idle, as defined by a 1 on RX_ER and an 0xE on RXD. The event is reported with the statistics generated on the next received frame. Only one false carrier condition can be detected and logged between frames.
Ethernet Communication Module increment when a packet is truncated to 1518 (non-VLAN) or 1522 (VLAN) bytes by MAXF.
Ethernet Control and Status registers Transmit byte counter (A060 06E0) Incremented by the number of bytes that were put on the wire, including fragments of frames that were involved with collisions. This count does not include preamble/ SFD or jam bytes.
Ethernet Communication Module Transmit excessive deferral packet counter (A060 06F8) Incremented for frames aborted because they were deferred for an excessive period of time (3036 byte times). D31:12 R Reset = Read as 0 Reserved D11:00 R/W Reset = 0x000 TEDF Transmit single collision packet counter (A060 06FC) Incremented for each frame transmitted that experienced exactly one collision during transmission.
Ethernet Control and Status registers Transmit total collision packet counter (A060 070C) Incremented by the number of collisions experienced during the transmission of a frame. Note: This register does not include collisions that result in an excessive collision count or late collisions. D31:12 R Reset = Read as 0 Reserved D11:00 R/W Reset = 0x000 TNCL Transmit jabber frame counter (A060 0718) Incremented for each oversized transmitted frame with an incorrect FCS value.
Ethernet Communication Module Transmit undersize frame counter (A060 0728) Incremented for every frame less than 64 bytes, with a correct FCS value. This counter also is incremented when a jumbo packet is aborted (see "TXAJ" on page 346) and the MAC is not checking the FCS (see "CRCEN" on page 352), because the frame is reported as having a length of 0 bytes.
Ethernet Control and Status registers Carry Register 1 Address: A060 0730 31 C164 30 29 28 C1127 C1255 C1511 27 26 25 C11K C1 MAX C1 MGV 10 9 C1RXP C1 RXU 15 14 13 12 11 C1 RPK C1 RFC C1 RMC C1 RBC C1 RXC 24 23 21 20 19 18 17 8 C1RAL 7 6 5 4 3 2 1 0 Rsvd C1 RCD C1 RCS C1 RUN C1 ROV C1 RFR C1 RJB Rsvd Bits Access Mnemonic Reset Description D31 R/C C164 0 Carry register 1 TR64 counter carry bit D30 R/C C1127 0 Carry register 1 TR127 counter carr
Ethernet Communication Module Bits Access Mnemonic Reset Description D05 R/C C1RCS 0 Carry register 1 RCSE counter carry bit D04 R/C C1RUN 0 Carry register 1 RUND counter carry register D03 R/C C1ROV 0 Carry register 1 ROVR counter carry bit D02 R/C C1RFR 0 Carry register 1 RFRG counter carry bit D01 R/C C1RJB 0 Carry register 1 RJBR counter carry bit D00 N/A Reserved N/A N/A Table 232: Carry Register 1 Carry Register 2 Address: A060 0734 31 30 29 28 27 26 25 24
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D10 R/C C2TBC 0 Carry register 2 TBCA counter carry bit D09 N/A Reserved N/A N/A D08 R/C C2TDF 0 Carry register 2TDFR counter carry bit D07 R/C C2TED 0 Carry register 2 TEDF counter carry bit D06 R/C C2TSC 0 Carry register 2 TSCL counter carry bit D05 R/C C2TMA 0 Carry register 2 TMCL counter carry bit D04 R/C C2TLC 0 Carry register 2 TLCL counter carry bit D03 R/C C2TXC 0 Carry register
Ethernet Communication Module Bits Access Mnemonic Reset Description D25 R/W M1MGV 1 Mask register 1 TRMGV counter carry bit mask D24:17 N/A Reserved N/A N/A D16 R/W M1RBY 1 Mask register 1 RBYT counter carry bit mask D15 R/W M1RPK 1 Mask register 1 RPKT counter carry bit mask D14 R/W M1RFC 1 Mask register 1 RFCS counter carry bit mask. Set this bit to 1 for RMII applications.
Ethernet Control and Status registers Carry Register 2 Mask register Address: A060 073C 31 30 29 28 27 26 25 24 23 22 21 20 Reserved 18 17 16 M2 JTB M2 TFC Not used M2 TOV 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 M2 TUN M2 TFG M2 TBY M2 TPK M2 TMC M2TBC Not used M2TDF M2 TED M2 TSC M2 TMA M2 TLC M2 TXC M2 TNC Bits Access Mnemonic Reset Description D31:20 N/A Reserved N/A N/A D19 R/W M2TJB 1 Mask register 2 TJBR counter carry bit mask D18 R/W M
Ethernet Communication Module RX_A Buffer Descriptor Pointer register Address: A060 0A00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RXAPTR 15 14 13 12 11 10 9 8 7 RXAPTR Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W RXAPTR 0x00000000 RX_A Buffer Descriptor Pointer Contains a pointer to the initial receive buffer descriptor for the A pool of buffers.
Ethernet Control and Status registers RX_C Buffer Descriptor Pointer register Address: A060 0A08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RXCPTR 15 14 13 12 11 10 9 8 7 RXCPTR Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W RXCPTR 0x00000000 RX_C Buffer Descriptor Pointer Contains a pointer to the initial receive buffer descriptor for the C pool of buffers.
Ethernet Communication Module Ethernet Interrupt Status register Address: A060 0A10 The Ethernet Interrupt Status register contains status bits for all of the Ethernet interrupt sources. Each interrupt status bit is assigned to either the RX or TX Ethernet interrupt; bits D25:16 are assigned to the RX interrupt and D06:00 are assigned to the TX interrupt. The bits are set to indicate an interrupt condition, and are cleared by writing a 1 to the appropriate bit.
Ethernet Control and Status registers Bits Access Mnemonic Reset Description D24 R/C RXOVFL_STAT 0 Assigned to RX interrupt. RX status FIFO overflowed. D23 R/C RXBUFC 0 Assigned to RX interrupt. I bit set in receive Buffer Descriptor and buffer closed. D22 R/C RXDONEA 0 Assigned to RX interrupt. Complete receive frame stored in pool A of system memory. D21 R/C RXDONEB 0 Assigned to RX interrupt. Complete receive frame stored in pool B of system memory.
Ethernet Communication Module Bits Access Mnemonic Reset Description D06 R/C STOVFL 0 Assigned to TX interrupt. Statistics counter overflow. Individual counters can be masked using the Carry Register 1 and 2 Mask registers. The source of this interrupt is cleared by clearing the counter that overflowed, and by clearing the associated carry bit in either Carry Register 1 or Carry Register 2 by writing a 1 to the bit. D05 R Not used 0 Always write as 0.
Ethernet Control and Status registers 31 30 29 28 27 26 Reserved 15 14 13 12 11 25 24 23 22 21 20 19 18 17 16 EN_RX OVFL_ DATA EN_RX OVFL_ STAT EN_ RX BUFC EN_RX DONE A EN_RX DONE B EN_RX DONE C EN_RX DONE D EN_ RXNO BUF EN_RX BUF FUL EN_ RXBR 9 8 7 6 5 4 3 10 EN_ST OVFL Reserved Not used EN_TX EN_TX BUF BUFC NR 2 1 0 EN_ TX DONE EN_ TX ERR EN_ TX IDLE Register bit assignment Bits Access Mnemonic Reset Description D31:26 N/A Reserved N/A N/A D25
Ethernet Communication Module TX Buffer Descriptor Pointer register Address: A060 0A18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Reserved TXPTR Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R/W TXPTR 0x00 Contains a pointer to the initial transmit buffer descriptor in the TX buffer descriptor RAM.
Ethernet Control and Status registers Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R/W TXRPTR 0x00 Contains a pointer to a buffer descriptor in the TX buffer descriptor RAM. Note: This pointer is the 8-bit physical address of the TX buffer descriptor RAM, and points to the first location of the four-location buffer descriptor. The byte offset of this buffer descriptor can be calculated by multiplying this value by 4.
Ethernet Communication Module Bits Access Mnemonic Reset Description D07:00 R TXERBD 0x00 Contains the pointer (in the TX buffer descriptor RAM) to the last buffer descriptor of a frame that was not successfully transmitted. TXERBD is loaded by the TX_WR logic when a transmit frame is aborted by the MAC or when the MAC finds a CRC error in a frame. TXERBD also is loaded if a buffer descriptor that is not the first buffer descriptor in a frame does not have its F bit set.
Ethernet Control and Status registers Register bit assignment Bits Access Mnemonic Reset Description D31:11 N/A Reserved N/A N/A D10:00 R RXAOFF 0x000 Contains an 11-bit byte offset from the start of the pool A ring. The offset is updated at the end of the RX packet, and will have the offset to the next buffer descriptor that will be used. RXAOFF can be used to determine where the RX_RD logic will put the next packet.
Ethernet Communication Module RX_C Buffer Descriptor Pointer Offset register Address: A060 0A30 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 Reserved RXCOFF Register bit assignment Bits Access Mnemonic Reset Description D31:11 N/A Reserved N/A N/A D10:00 R RXCOFF 0x000 Contains an 11-bit byte offset from the start of the pool C ring.
Ethernet Control and Status registers Register bit assignment Bits Access Mnemonic Reset Description D31:11 N/A Reserved N/A N/A D10:00 R RXDOFF 0x000 Contains an 11-bit byte offset from the start of the pool D ring. The offset is updated at the end of the RX packet, and will have the offset to the next buffer descriptor that will be used. RXDOFF can be used to determine where the RX_RD logic will put the next packet.
Ethernet Communication Module RX Free Buffer register Address: A060 0A3C So the RX_RD logic knows when the software is freeing a buffer for reuse, the software writes to the RXFREE register each time it frees a buffer in one of the pools. RXFREE has an individual bit for each pool; this bit is set to 1 when the register is written. Reads to RXFREE always return all 0s.
Ethernet Control and Status registers TX buffer descriptor RAM Address: A060 1000 The TX buffer descriptor RAM holds 64 transmit buffer descriptors on-chip. Each buffer descriptor occupies four locations in the RAM, and the RAM is implemented as a 256x32 device.
Ethernet Communication Module Sample hash table code This sample C code describes how to calculate hash table entries based on 6-byte Ethernet destination addresses and a hash table consisting of two 32-bit registers (HT1 and HT2). HT1 contains locations 31:0 of the hash table; HT2 contains locations 63:32 of the hash table. The pointer to the hash table is bits [28:23] of the Ethernet destination address CRC.
Sample hash table code // create hash table for MAC address eth_make_hash_table (hash_table); (*MERCURY_EFE) .ht2.bits.data = SWAP32(hash_table[1]); (*MERCURY_EFE) .ht1.bits.data = SWAP32(hash_table[0]); } / * * * Function: void eth_make_hash_table (WORD32 *hash_table) * * Description: * * This routine creates a hash table based on the CRC values of * the MAC addresses setup by set_hash_bit().
Ethernet Communication Module { set_hash_bit ((BYTE *) hash_table, calculate_hash_bit (mca_address [index])); } } / * * * Function: void set_hash_bit (BYTE *table, int bit) * * Description: * * This routine sets the appropriate bit in the hash table.
Sample hash table code * Function: int calculate_hash_bit (BYTE *mca) * * Description: * This routine calculates which bit in the CRC hash table needs * to be set for the MERCURY to recognize incoming packets with * the MCA passed to us.
Ethernet Communication Module mcap++; for (bit_index = 0; bit_index < 16; bit_index++) { bx = (WORD16) (crc >> 16); /* get high word of crc*/ bx = rotate (bx, LEFT, 1); /* bit 31 to lsb*/ bx ^= bp; /* combine with incoming*/ crc <<= 1; /* shift crc left 1 bit*/ bx &= 1; /* get control bit*/ if (bx) /* if bit set*/ { crc ^= POLYNOMIAL; /* xero crc with polynomial*/ } crc |= bx: /* or in control bit*/ bp = rotate (bp, RIGHT, 1); } } // CRC calculation done.
Sample hash table code 402 NS9750 Hardware Reference
PCI-to-AHB Bridge C H A P T E R 7 T he PCI-to-AHB bridge provides connections between PCI-based modules/devices and the NS9750 AHB bus. Important: This chapter presumes knowledge of PCI system standards and architecture, and explains how PCI works in relation to the AHB bus. If you have questions regarding PCI terminology or concepts, please refer to your PCI documentation.
About the PCI-to-AHB Bridge About the PCI-to-AHB Bridge The PCI-to-AHB bridge provides these features: Supports PCI specification 2.1 and 2.
PCI-to-AHB Bridge PCI-to-AHB bridge functionality Figure 71 shows the PCI-to-AHB bridge. Downstream transactions are those initiated on the AHB bus; upstream transactions are those initiated on the PCI bus. AHB master PCI target write buffer 32x32 AHB master read buffer 16x32 PCI bus Bus/ Req grant PCI bus arbiter Note: The PCI Bus arbiter is not part of the bridge. It is a separate module shown here for illustration. It's use is optional.
About the PCI-to-AHB Bridge being sent back to the PCI bus. The AHB master interface supports both single and burst transactions. AHB slave/target interface The AHB slave/target interface block controls the AHB target access to the bridge, and is used for reads and writes to the PCI bus that are initiated on the AHB bus. The requests are transferred to the PCI master interface. Writes are posted in the dual 64-byte AHB target write buffer and then transferred to the dual 64-byte PCI master write buffer.
PCI-to-AHB Bridge PCI bus arbiter The PCI bus arbiter (also referred to as PCI arbiter), although embedded in NS9750, is not part of the PCI-to-AHB bridge protocol. See "PCI bus arbiter," beginning on page 418, for information about the PCI arbiter. The arbiter’s use is optional. Cross-bridge transaction error handling The PCI-to-AHB bridge supports several error-handling mechanisms. All mechanisms can cause an interrupt to the system unless they are masked.
About the PCI-to-AHB Bridge bit in the PCI Status register is set. For address parity errors, the SIGNALED TARGET ABORT bit in the PCI Status register is set. DETECTED PARITY ERROR For data parity checking on writes, the entire burst is discarded if any word in the burst has a parity error.
PCI-to-AHB Bridge window size of each Base Address register is hardwired (see Table 257 on page 417), but each register can be enabled or disabled using the ENBAR0–ENBAR5 bits in the PCI Miscellaneous Support register (see page 426) in the PCI arbiter. The bridge supports PCI to AHB memory address translation using the PCI Bridge PCI to AHB Memory Address Translate 0/1(see page 439) and PCI Bridge Address Translation Control (see page 441) registers.
About the PCI-to-AHB Bridge Bridge receives a target abort (RTA, see "Received target abort" on page 415) Bridge signals a target abort (STA, see "Signaled target abort" on page 415) Bridge master finds a parity error on read data or detects the target asserting a master data parity error (PERR#, see "Master data parity error" on page 415) and the parity error response bit in the PCI Command register (see page 414) is set.
PCI-to-AHB Bridge Endian configuration The PCI bus is defined as little endian and the AHB bus can be defined as either Big or little endian. The PCI-to-AHB bridge supports byte-swapping only when the AHB bus is configured as a big endian bus. Byte-swapping is selected using the endian mode bit in the Miscellaneous System Configuration register (see "Miscellaneous System Configuration and Status register," beginning on page 296). Table 252 shows the byteswapping scheme used.
About the PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D23:16 R/W BUS_NUMBER 0x00 Target PCI bus number Bus 0. Considered a local bus, so a Type 0 configuration is performed. All other bus numbers. Result in a Type 1 cycle that targets an external bus (that is, a bus on the other side of a PCI-to-PCI bridge).
PCI-to-AHB Bridge Bridge Configuration registers Table 254 shows the standard PCI configuration registers that are supported by the PCI-to-AHB bridge. These registers can be 8-, 16-, or 32-bits wide, as indicated in the table. The size of the transfer on the AHB bus determines which bytes are written. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed. The registers are described briefly in this chapter.
About the PCI-to-AHB Bridge Register number 1 [31:24] [23:16] [15:08] [07:00] These entries are standard read-only PCI configuration registers that are initialized using registers in the PCI arbiter (see "PCI bus arbiter," beginning on page 418). Table 254: PCI/bridge configuration registers PCI Vendor ID register Read-only value. To change this value, use the VENDOR_ID field in the PCI Configuration 0 register in the PCI arbiter (see page 428). PCI Device ID register Read-only value.
PCI-to-AHB Bridge PCI Status register Table 256 describes the PCI Status register fields. Bits Access Mnemonic Reset Description D15 R/C DPE 0 Detected parity error Device detected parity error. Used as an interrupt source to AHB bus. D14 R/C SERR# 0 Signaled system error Device generated system error (SERR#). Used as an interrupt source to AHB bus. D13 R/C RMA 0 Received master abort Master aborted transaction. Used as an interrupt source to AHB bus.
About the PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D07 Hard-wired to 1 FBBC 1 Fast back-to-back capable 0 No support 1 Support Device supports fast back-to-back transactions as a target only. D06 N/A Not used 0 Hardwired to 0. D05 Hard-wired to 0 BS66 0 66MHz capable Bus speed: 0 33 MHz 1 66MHz D04:00 N/A Not used 0 Always set to 0. Table 256: PCI Status register PCI Revision ID register Read-only value.
PCI-to-AHB Bridge PCI BIST register Read-only value, hardwired to 0x0. PCI Base Address registers [5:0] The PCI-to-AHB bridge supports the six Base Address registers defined by PCI. Table 257 defines the memory space size decoded by each register.
PCI bus arbiter PCI Subsystem ID register Read-only value. To change this value, use the SUBSYSTEM_ID field in the PCI Configuration 2 register (see page 430) in the PCI arbiter. PCI Expansion ROM register Read-only value, hardwired to 0x00000000. PCI Interrupt Line register Read/write value indicating to which line of an interrupt controller the PCI interrupt generated by the bridge is connected. This register is used only in those systems in which NS9750 is not handling PCI interrupts.
PCI-to-AHB Bridge NS9750 can be configured to use either the embedded PCI arbiter or an external arbiter through the bootstrap initialization scheme used during powerup (see "Bootstrap initialization" on page 272). The RTCK pin selects the source of the arbiter: The internal arbiter is used if RTCK = 1. If a pulldown resistor is placed on the RTCK bit, an external arbiter is used.
PCI bus arbiter If there are no new requesters when the current bus master completes its transaction, the bus ownership stays with the most recent bus master (bus parking). If a REQ# is asserted from any of the other masters, there must be a one clock cycle delay between the negation of the GNT# to the parked bus master and the assertion of the GNT# to the bus master requesting the bus.
PCI-to-AHB Bridge Address Offset Register Description 0xA030 0000 PARBCFG PCI Arbiter Configuration 0xA030 0004 PARBINT PCI Arbiter Interrupt Status 0xA030 0008 PARBINTEN PCI Arbiter Interrupt Enable 0xA030 000C PMISC PCI Miscellaneous Support 0xA030 0010 PCFG0 PCI Configuration 0 0xA030 0014 PCFG1 PCI Configuration 1 0xA030 0018 PCFG2 PCI Configuration 2 0xA030 001C PCFG3 PCI Configuration 3 0xA030 0020 PAHBCFG PCI Bridge Configuration 0xA030 0024 PAHBERR PCI Bridge AHB Err
PCI bus arbiter Address Offset Register 0xA030 1014–0xA030 1FFC Table 259: PCI arbiter register map 422 NS9750 Hardware Reference Description Reserved (all read accesses return 0x0 value)
PCI-to-AHB Bridge PCI Arbiter Configuration register Address: A030 0000 The PCI Arbiter Configuration register enables and disables each of the three external PCI bus masters. The internal PCI-to-AHB bridge is always enabled.
PCI bus arbiter Bits Access Mnemonic Reset Description D00 R PCI_CTL_RSC_n N/A PCI_CENTRAL_RSC_n input to NS9750 (NS9750 has internal pulldown) 0 NS9750 provides PCI central resource functions (pulldown) 1 NS9750 does not provide PCI central resource functions Table 260: PCI Arbiter Configuration register PCI Arbiter Interrupt Status register Address: A030 0004 The PCI Arbiter Interrupt Status register reports broken masters (that is, masters that do not respond in 16 clocks after being granted
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D05 R/C CCLKRUN 0 Restart CardBus clock Used for CardBus Applications only. Indicates that an external CardBus card has asserted CardBus CCLKRUN# to request that the CardBus clock be restarted. D04 R/C PCISERR 0 An SERR signal has been received from an external PCI agent.
PCI bus arbiter BIts Access Mnemonic Reset Description D05 R/W EN_CCLKRUN 0 Enable CCLKRUN# interrupt 0 Disable (default) 1 Enable D04 R/W EN_PCISERR 0 Enable SERR received from external PCI agent 0 Disable (default) 1 Enable D03 R/W EN_PBRK_M3 0 Enable external master 3 broken 0 Disable (default) 1 Enable D02 R/W EN_PBRK_M2 0 Enable external master 2 broken 0 Disable (default) 1 Enable D01 R/W EN_PBRK_M1 0 Enable external master 1 broken 0 Disable (default) 1 Enable D00 R/W
PCI-to-AHB Bridge 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 3 2 1 0 Reserved 15 14 13 12 11 10 Reserved 9 8 7 6 5 4 EN_ BAR5 EN_ BAR4 EN_ BAR3 EN_ BAR2 EN_ BAR1 EN_ BAR0 Reserved INTA2 PCI Register bit assignment Bits Access Mnemonic Reset Description D31:10 Read only; hard-wired to 0 Reserved N/A N/A D09 R/W EN_BAR5 0 Enable bridge PCI Base Address register 5 0 Disable (default) 1 Enable Note: D08 R/W EN_BAR4 0 Enable bridge PCI Base Addre
PCI bus arbiter Bits Access Mnemonic Reset Description D06 R//W EN_BAR2 0 Enable bridge PCI Base Address register 2 0 Disable (default) 1 Enable Note: D05 R/W EN_BAR1 0 Enable bridge PCI Base Address register 1 0 Disable (default) 1 Enable Note: D04 R/W EN_BAR0 0 Although BAR_x can still be accessed when EN_BAR2 is 1, the address range defined by BAR_x will not be decoded. Although BAR_x can still be accessed when EN_BAR1 is 1, the address range defined by BAR_x will not be decoded.
PCI-to-AHB Bridge Change these fields only during system initialization, when there is no PCI activity. In a system where NS9750 is not the host, these fields must be programmed within 225 PCI clocks of RST# being negated. This is the time allowed from RST# negated to the first configuration cycle on the PCI bus.
PCI bus arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CLASS_CODE 15 14 13 12 11 10 9 8 7 CLASS_CODE REVISION_ID Register bit assignment Bits Access Mnemonic Reset Description D31:08 R/W CLASS_CODE 0x060000 Class code value Value to be inserted into PCI Class Code register. Defaults to class code for a host/PCI bridge (0x060000). D07:00 R/W REVISION_ID 0x00 Revision ID value Value to be inserted into the PCI Revision ID register.
PCI-to-AHB Bridge Register bit assignment Bits Access Mnemonic Reset Description D31:16 R/W SUBSYSTEM_ID 0x0000 Subsystem ID value Value to be inserted into the PCI Subsystem ID register. Defaults to 0x0000. D15:00 R/W SUBVENDOR_ID 0x0000 Subvendor ID value Value to be inserted into the PCI Subvendor ID register. Defaults to 0x0000.
PCI bus arbiter Bits Access Mnemonic Reset Description D23:16 R/W MAX_LATENCY 0x00 Max latency value Value to be inserted into the PCI Max_Lat register. Defaults to 0x00. D15:08 R/W MIN_GRANT 0x00 Min grant value Value to be inserted into the PCI Min_Gnt register. Defaults to 0x00. D07:00 R/W INTERRUPT_PIN 0x01 Interrupt pin value Value to be inserted onto the PCI Interrupt Pin register. Defaults to 0x01, which is the encoding for INTA#.
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D01:00 R/W AHBBRST 0x1 AHB burst length control Determines the type of burst cycles done when the bridge acts as AHB master: 00 16 01 32 (default) 10 64 11 Reserved Table 268: PCI Bridge Configuration register PCI Bridge AHB Error Address register Address: A030 0024 The PCI Bridge AHB Error Address register stores the address of the AHB transaction that received an AHB ERROR response.
PCI bus arbiter The PCI Bridge PCI Error Address register stores the address of the PCI transaction that received a PCI bus error response. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 PCIEADR 15 14 13 12 11 10 9 8 7 PCIEADR Register bit assignment Bits Access Mnemonic Reset Description D31:00 R PCIEADR 0x00000000 PCI error address Holds the PCI address that caused an error, when any of the PCI error bits are set in the PCI Status register.
PCI-to-AHB Bridge Register bit assignment Bits Access Mnemonic Reset Description D31:01 Hardwired to 0 Reserved N/A N/A D00 R/C AHBERR 0 AHB bus error Table 271: PCI Bridge Interrupt Status register PCI Bridge Interrupt Enable register Address: A030 0030 The PCI Bridge Interrupt Enable register stores the enables for all interrupt sources.
PCI bus arbiter Bits Access Mnemonic Reset Description D13 R/W PRXMAEN 0 PCI received master abort enable 0 Interrupt disabled 1 Interrupt enabled Bit 13 of PCI Status register D12 R/W PRXTARN 0 PCI received target abort enable 0 Interrupt disabled 1 Interrupt enabled Bit 12 of PCI Status register D11 R/W PSIGTAEN 0 PCI signaled target abort enable 0 Interrupt disabled 1 Interrupt enabled Bit 11 of PCI Status register D10:09 Hardwired to 0 Reserved N/A N/A D08 R/W PMPERREN 0 PC
PCI-to-AHB Bridge PCI Bridge AHB to PCI Memory Address Translate 0 register Address: A030 0034 The PCI Bridge AHB-to-PCI Memory Address Translate 0 register translates the AHB addresses sent to the PCI-to-AHB bridge to the appropriate PCI memory addresses.
PCI bus arbiter PCI Bridge AHB to PCI Memory Address Translate 1 register Address: A030 0038 The PCI Bridge AHB-to-PCI Memory Address Translate 1 register translates the AHB addresses sent to the PCI-to-AHB bridge to the appropriate PCI memory addresses.
PCI-to-AHB Bridge PCI Bridge AHB-to-PCI IO Address Translate register Address: A030 003C The PCI Bridge AHB-to-PCI IO Address Translate register translates the AHB addresses sent to the PCI-to-AHB bridge to the appropriate PCI IO addresses.
PCI bus arbiter Register bit assignment Bits Access Mnemonic Reset Description D31:30 Hardwired to 0 Reserved N/A N/A D29:20 R/W MALT3VAL 0x000 Bits [31:22] of AHB address if PCI address matches BAR3. D19:12 R/W MALT2VAL 0x00 Bits [31:24] of AHB address if PCI address matches BAR2. D11:10 Hardwired to 0 Reserved N/A N/A D09:04 R/W MALT1VAL 0x00 Bits [31:26] of AHB address if PCI address matches on BAR1.
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D25:12 R/W MALT5VAL 0x0000 Bits [31:18] of AHB address if PCI address matches BAR5. D11:00 R/W MALT4VAL 0x000 Bits [31:20] of AHB address if PCI address matches BAR4.
PCI bus arbiter Bits Access Mnemonic Reset Description D00 R/W PALT_EN 0 Enable AHB-to-PCI address translation for both PCI memory and IO space 0 Do not translate AHB addresses. The same addresses are used for both PCI and AHB. 1 Translate AHB addresses per the PALTxxVAL fields in the PCI Bridge AHB-to-PCI Memory Address Translate registers (see page 437 and page 438) and the PCI Bridge AHB-to-PCI IO Address Translate register (see page 439).
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D29 R/W CMS_V3_SKT 0 Allows software to control the V3_SKT bit in the CardBus Socket Present State register. When set, indicates that VCC=3.3 volts can be supplied to the socket. D28 R/W CMS_V5_SKT 0 Allows software to control the V5_SKT bit in the CardBus Socket Present State register. When set, indicates that VCC=5 volts can be supplied to the socket.
PCI bus arbiter Bits Access Mnemonic Reset Description D21 R/W CMS_DATA_LOST 0 Allows software to control the DATA_LOST bit in the CardBus Socket Present State register. When set, indicates that the external card was removed from the socket while the interface was active, and data may have been lost. D20 R/W CMS_NOTA_CARD 0 Allows the software to control the NOTA_CARD bit in the CardBus Socket Present State register. When set, indicates that an unsupported card is inserted in the socket.
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D15 R/W CMS_CCD1 0 Allows the software to control the CCD1 bit in the Cardbus Socket Present State register. Reflects the current state of the CardBus CCD#1 pin: 0 A card is inserted in the socket. 1 No card is in the socket. Because CCD#1 can be shorted to either CVS2 or CVS1, the value here applies when CVS[2:1] are both 0.
PCI bus arbiter Bits Access Mnemonic Reset Description D04 R/W CVS1 0 Value driven out on CVS1 pin during socket interrogation. D03 R CCLK_STOP_NACK 0 Response to request to negate CardBus CCLKRUN# using CCLKRUN# protocol 0 CCLKRUN# request not refused yet. Check CCLK_STOP_ACK to determine whether CCLKRUN# is negated. 1 CCLKRUN# not negated because the external CardBus device will not allow it.
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D31:04 Hardwired to 0 Reserved N/A N/A D03 R/C PWR_CHG 0 Set when the PWR_CYC bit in the CardBus Socket Present State register changes. This bit can also be set by writing a 1 to the FPWR_CHG bit in the CardBus Socket Force Event register. D02 R/C CCD2_CHG 0 Set when the CCD#2 signal changes. Changes during card interrogation (when the INTERROGATE bit is set to 1 in the CardBus Miscellaneous Support register) are ignored.
PCI bus arbiter 31 30 29 28 27 26 25 24 23 22 21 20 6 5 4 19 18 17 3 2 1 16 Reserved 15 14 13 12 11 10 9 8 7 PWR_ CCD2_ CCD1_ CHG_ CHG_ CHG_ EN EN EN Reserved 0 CSTS CHG_ CHG Register bit assignment Bits Access Mnemonic Reset Description D31:04 Hardwired to 0 Reserved N/A N/A D03 R/W PWR_CHG_EN 0 Power cycle interrupt enable 0 Interrupt disabled 1 Interrupt enabled D02 R/W CCD2_CHG_EN 0 CCD2 change interrupt enable 0 Interrupt disabled 1 Interrupt enabl
PCI-to-AHB Bridge 31 30 29 28 27 YV_ SKT XV_ SKT V3_ SKT V5_ SKT ZV_ SUPP 15 14 Reserved 26 25 24 23 22 21 20 19 18 17 2 1 16 Reserved 13 12 11 10 YV_ CARD XV_ CARD V3_ CARD V5_ CARD 9 8 7 BAD_ DATA_ NOTA_ VCC_ LOST CARD REQ 6 5 4 3 CINT CB_ CARD CARD_ 16 PWR_ CYC CCD2 CCD1 0 CSTS CHG Register bit assignment Bits Access Mnemonic Reset Description D31 R YV_SKT 0 When set, indicates that VCC=Y.Y volts can be supplied to the socket.
PCI bus arbiter Bits Access Mnemonic Reset Description D11 R V3_CARD 0 When set, indicates that the card inserted into the socket supports VCC=3.3 volts. This bit can also be set by writing a 1 to the FV3_CARD bit in the CardBus Socket Force Event register. D10 R V5_CARD 0 When set, indicates that the card inserted into the socket supports VCC=5 volts. This bit can also be set by writing a 1 to the FV5_CARD bit in the CardBus Socket Force Event register.
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D04 R CARD_16 0 When set, indicates that a 16-bit PC card is inserted in the socket. This bit can also be set by writing a 1 to the FCARD_16 bit in the CardBus Socket Force Event register when a card is not inserted in the socket. D03 R PWR_CYC 0 When set, indicates that the socket is powered up. When cleared, this bit indicates that the socket is powered down.
PCI bus arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 5 4 3 16 Reserved 15 14 13 12 11 10 9 Rsvd CV_ TEST FYV_ CARD FXV_ CARD FV3_ CARD FV5_ CARD FBAD_ VCC_ REQ 8 7 6 F F DATA_ NOTA_ LOST CARD Rsvd 2 1 0 F F F FCTS 16 CHG CHG CHG FPWR_ FCB_ CCD2_ CCD1_ SCHG_ CARD_ CHG CARD Register bit assignment Bits Access Mnemonic Reset Description D31:15 N/A Reserved N/A N/A D14 W CV_TEST N/A Requests that the card interrogation procedure be run ag
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D06 N/A Reserved N/A N/A D05 W FCB_CARD N/A Sets the CB_CARD bit in the CardBus Socket Present State register. If a card is in the socket (that is, CMISC_CCD[1:0]=00 in the CardBus Miscellaneous Support register), writes to this bit are ignored. D04 W FCARD_16 N/A Sets the CARD_16 bit in the CardBus Socket Present State register.
PCI bus arbiter CardBus Socket Control register Address: A030 1010 The CardBus Socket Control register is used only for CardBus applications.
PCI-to-AHB Bridge Bits Access Mnemonic Reset Description D02:00 R/W VPP_CTL 000 Socket VPP/Core control 000 0V 001 12 V 010 5V 011 3.3 V 100 Reserved 101 Reserved 110 1.8 V 111 Reserved Table 284: CardBus Socket Control register www.digiembedded.
PCI system configurations PCI system configurations REQ1# REQ2# REQ3# PCI REQ IN NS9750 can be connected to the PCI bus using an embedded (internal) or external PCI bus arbiter. Figure 72 shows how NS9750 is connected to the PCI bus for a typical system application using the embedded PCI bus arbiter, and where the NS9750 provides the central resource function (see "PCI central resource functions" on page 458). Up to three external masters are supported.
PCI-to-AHB Bridge The internal PCI arbiter is selected when the RTCK pin is set to 1 during powerup. Because the RTCK pad has a weak internal pullup, no external components are required to select the internal PCI arbiter. Figure 73 shows how NS9750 is connected to the PCI bus for a typical application using an external PCI bus arbiter, and where the NS9750 does not provide the PCI central resource functions (see "PCI central resource functions" on page 458).
PCI system configurations Device selection for configuration The NS9750 IDSEL pin is used as a chip select during PCI configuration transactions. If the bridge’s configuration registers are being programmed using the AHB bus, NS9750 must be set as Device 0 (see Figure 72, "System connections to NS9750 — Internal arbiter and central resources," on page 456, which shows IDSEL connected to AD[11] and which configures NS9750 as PCI Device 0).
PCI-to-AHB Bridge AD[31:0], C/BE[3:0], and PAR are driven low when RST# is asserted, to keep the signals from floating. www.digiembedded.
PCI system configurations When the PCI_CENTRAL_RSC_n pin is pulled high (see Figure 73), these functions operate differently: RST# is configured as an input, and must be supplied by the system. In this situation, RST# is used as another system reset to NS9750; that is, either reset_n or RST# can reset NS9750, and both must be negated to take NS9750 out of reset. SERR# is configured as output. AD[31:0], C/BE[3:0], and PAR are tri-stated when RST# is asserted.
PCI-to-AHB Bridge Important: Note that in cases where NS9750 provides the PCI clock, the PCI clock connection to the NS9750 must still be made external to the NS9750, as shown in Figure 73 (that is, connect PCI_clk_out to PCI_clk_in). This is done to minimize the clock skew between the NS9750 and external PCI devices. CardBus Support NS9750 can support 32-bit CardBus applications using the existing PCI port and existing PCI-to-AHB bridge IP.
CardBus Support VCC RCCD2 VCC RCCD1 VCC RCRUN REQ3# REQ2# PCI PCI CLK CLK OUT IN AD Rs Rs CONTROL SERR# Rs RST# Rs GNT1# INTA# Rs INTB# INTC# VCC 3 RCVS 3 RCVS GNT2# CVS1 GNT3# CVS2 IDSEL INTD# GPIO RTCK 4 GPIO PCI_CENTRAL_RSC_n 4 CAD CAD CONTROL2 CONTROL CSERR#2 CSERR# CRST# CRST# CREQ#2 REQ1# NS9750 CCLK CCD1 CCD2 CGNT# CREQ# 2 CGNT# CINT#2 CINT# CCLKRUN# CCLKRUN# CSTSCHG CSTSCHG CVS1 CVS2 CVS1_DET CVS2_DET CARDBUS SOCKET RSTS BOOT_STRAP[1] GPIO GPIO GPIO V
PCI-to-AHB Bridge Notes: The power controller is required only for applications that support hot-insertion 1 and hot-removal of the CardBus card. This requires additional components to isolate NS9750 from CardBus. 2 The system must provide external pullup per PCI specification. CAD, C/BE, and PAR do not require pullups. 3 Voltage detection signal optional for embedded system. 4 Pins not connected because internal resistors tie these to the appropriate state.
CardBus Support PCI Signal CardBus Signal CardBus type Comments REQ2# CCD1 Input Card detect pin. Pulled up by system when socket is empty and pulled low when the external CardBus device is present in the socket. REQ3# CCD2 Input Card detect pin. Pulled up by system when socket is empty and pulled low when the external CardBus device is present in the socket. N/A CVS1_DET Input Voltage sense detect pin. Can be any GPIO input.
PCI-to-AHB Bridge CardBus Socket Event (see "CardBus Socket Event register" on page 446) CardBus Socket Mask (see "CardBus Socket Mask register" on page 447) CardBus Socket Present State (see "CardBus Socket Present State register" on page 448) CardBus Socket Force Event (see "CardBus Socket Force Event register" on page 451) CardBus Socket Control (see "CardBus Socket Control register" on page 454) CardBus interrupts The dedicated CINT# signal on the CardBus is connected directly to the interrupt control
CardBus Support 466 NS9750 Hardware Reference
BBus Bridge C H A P T E R 8 T he NS9750 ASIC contains two busses that interconnect the peripherals. The high speed peripherals reside on the AMBA AHB bus. The low speed peripherals reside on the Digi proprietary BBus. The main function of the BBus bridge is to connect the main AHB bus to the proprietary Digi BBus. Both bus interfaces have a master and a slave interface.
BBus bridge functions BBus bridge functions The Digi BBus is a low-speed secondary bus that operates at half the AHB clock frequency. The BBus interface houses the slower serial interfaces for USB, IEEE 1284, SPI, and UART, as well as dedicated BBus DMA control, to offload some of the bandwidth demands of the primary AHB bus. The BBus bridge controls the flow of data between the AHB and BBus interfaces. The BBus bridge provides these functions: BBus arbitration and multiplexing.
BBus Bridge Figure 75 shows the four functions of the BBus bridge in relation to the AHB bus and the BBus. NS9750 ASIC AHB Module B .... AHB Module N External Mem #1 AHB Memory Controller AMBA AHB Bus Bridge BBUS Control AHB DMA SPI Boot BBUS Bridge Module ... AHB Module A External Mem #N NetSilicon BBUS BBUS Module A BBUS Module B ....
Bridge control logic AMBA AHB Bus External DMA Handshake AHB Master AHB Slave AHB DMA Controller User Interface 1 Entry AHB Retiming Fifo SPI-BOOT Controller 4 Entry BBUS Retiming Fifo BBUS Master BBUS Control and Mux BBUS Slave NetSilicon BBUS BBUS arbitration with other masters and slaves Figure 76: BBus bridge block diagram Notes: The AHB bus and BBus clock domains are asynchronous to each other.
BBus Bridge DMA accesses There are two DMA controllers on the NS9750 BBus. One DMA controller services all BBus peripherals except the USB device; the other is dedicated to the USB device. Each DMA controller contains 16 channels that perform both DMA read and DMA write transactions. Note: The USB host is a bus mastering BBus peripheral. DMA memory-to-peripheral transfers (DMA read). DMA read transactions begin with the DMA controller arbitrating for BBus control.
BBus control logic BBus control logic BBus control logic consists of a round-robin arbiter to select a new master, the multiplexing logic to provide the new master’s signals to the BBus slaves, and address decoding to select the target BBus slave. BBus bridge masters and slaves BBus bridge arbitration allows each bus master to control the bus in a round-robin manner. If a bus master does not require the bus resources when its turn comes around, that bus master is skipped until the next round-robin slot.
BBus Bridge Cycles and BBus arbitration During a normal cycle, each bus master cycle is allowed only one read/write cycle if another bus master is waiting. There are two exceptions to this rule: burst transactions and read-modify-write transactions. In a burst transaction, the master can perform more than one read or write cycle. In a read-modify-write transaction, the bus master performs one read and write cycle to the same location.
Two-channel AHB DMA controller (AHB bus) Two-channel AHB DMA controller (AHB bus) Each DMA channel moves data from the source address to the destination address. Transfers can be specified as burst-oriented to maximize AHB bus efficiency. All transfers are executed in two steps: 1 Data is moved from the source address to an 8-entry buffer in the DMA control logic. 2 Data is moved from the 8-entry buffer to the destination address. These steps are repeated until the DMA transfer is complete.
BBus Bridge When the current descriptor is retired, the next descriptor is accessed from a circular buffer. Each DMA buffer descriptor requires four 32-bit words to describe a transfer. Circular buffers of 1024 bytes contain multiple buffer descriptors. The first buffer descriptor address is provided by the DMA channel’s Buffer Descriptor Pointer register. Subsequent buffer descriptors are found adjacent to the first descriptor. The final buffer descriptor is defined with its W bit set.
Two-channel AHB DMA controller (AHB bus) Field/Section Description W The wrap bit. When set, this bit tells the DMA controller that this is the last buffer descriptor within the continuous list of descriptors. The next buffer descriptor is found using the initial DMA channel buffer descriptor pointer. When the wrap bit is not set, the next buffer descriptor is found using an offset of 0x10 from the current buffer descriptor. I The interrupt bit.
BBus Bridge Peripheral DMA read access Figure 78 and Figure 79 show how the DMA engine performs read accesses of an external peripheral. The CLK signal shown is for reference, and its frequency is equal to 1/2 the speed grade of the part. The rising edge of the READ_EN signal coincident with the assertion of the chip select signal must cause the peripheral to place the next quantum of data on the bus. The width of the READ_EN signal is always equal to one reference CLK period.
Two-channel AHB DMA controller (AHB bus) CLK CS# READ_EN DQ DATA0 DATA1 Figure 79: Peripheral DMA burst read access Peripheral DMA write access Figure 80 and Figure 81 show how the DMA engine performs write accesses of an external peripheral. The clock signal shown is for reference, and its clock frequency is equal to 1/2 the speed grade of the part. Data should be written on the rising edge of the WE# signal.
BBus Bridge CLK CS# WE# DATA0 DQ DATA1 DATA2 Figure 81: Peripheral DMA burst write access Peripheral REQ signaling An external peripheral indicates that it can accept or provide data by asserting its REQ signal. The AHB DMA controller fully processes one buffer descriptor for each assertion of the external peripheral’s REQ signal. The AHB DMA controller state machine executes these steps for each assertion of the REQ signal. 1 Fetch the next buffer descriptor in the list from system memory.
Two-channel AHB DMA controller (AHB bus) Design Limitations The AHB DMA logic contains several design limitations. Carefully consider these limitations when making system level implementation decisions: The AHB DMA control logic is designed to operate on four-byte quantities, which limits the minimum number of accesses that the memory controller can perform on narrow external peripherals. Accesses to an 8-bit peripheral will always occur in multiples of four.
BBus Bridge transferring data in non-DMA mode do not contribute to the calculation. The worst case AHB DMA response latency occurs when all of the BBus peripherals perform these operations within several microseconds of each other: Move the remaining data in or out of the data buffer. Close the buffer descriptor. Open a new buffer descriptor. Begin processing the new data buffer. This can be two steps for a transmitter. Two AHB bandwidth calculations are defined here.
Two-channel AHB DMA controller (AHB bus) Static RAM chip select configuration The AHB DMA controller accesses an external peripheral using the external memory bus and one of the static RAM chip select signals (st_cs_n[N]). This table describes how to program the static RAM chip select control registers for access using the AHB DMA controller. Fields not explicitly listed should be left in the reset state. Fields listed but not defined must be defined by the user.
BBus Bridge Interrupt aggregation All the peripherals on the BBus, as well as AHB DMA channels 1 and 2 in the BBus bridge, can interrupt the CPU when attention is required. These interrupts are aggregated in the BBus bridge, and a single interrupt is presented to the System Control Module on the bbus_int signal. This function is performed in the BBus bridge because it allows the processor to quickly identify which BBus peripheral(s) is requesting attention.
SPI-EEPROM boot logic SPI-EEPROM boot logic SPI-EEPROM boot logic is enabled by strapping off the boot_cfg pins to the boot from SDRAM setting in the Miscellaneous System Configuration and Status register. Table 291 shows the related boot settings.
BBus Bridge Calculation and example This equation calculates the amount of time, in seconds, required to copy the contents of the SPI-EEPROM to external memory: Time = (1 / freq) * EEPROMSIZE Example SPI master clock frequency = 1.5 MHz SPI-EEPROM = 256 Kb Time for operation to complete = 175 ms Serial Channel B configuration When exiting the power-on reset state, serial channel B is in SPI master mode, which facilitates communication with the external SPI-EEPROM.
SPI-EEPROM boot logic Memory Controller configuration Note: See your ARM documentation for complete information about the memory controller. The memory controller exits the reset state in non-operational mode. This requires the SPI-EEPROM boot logic to configure the memory controller as well as the external SDRAM before any memory access.
BBus Bridge EEPROM entry Description SDRAM config All SDRAM components contain a Mode register, which has control information required to successfully access the component.
SPI-EEPROM boot logic EEPROM entry Description DynamicConfig0 Field B (buffer enable, in the DynamicConfig0 register) should be set to 0 (buffers disabled). The buffers will be enabled by hardware as part of the boot process. See your ARM documentation. DynamicRasCas0 See the Memory Controller chapter. Reserved The remaining bytes are undefined.
BBus Bridge 4 The state machine enters a loop where four NOP words are written to the Fifo Data register and four words are read from the Fifo Data register. The RXFDB and RRDY fields are continuously monitored in Status Register A. The Fifo Data register is read only when a valid word is present. 5 The CPU is taken out of reset and serial channel B is placed into reset. Normal operation begins with the ARM fetching an instruction from system memory address 0x00000000.
BBus Bridge Control and Status registers BBus Bridge Control and Status registers The BBus configuration registers are located at base address 0xA040.0000. All configuration registers are accessed with zero wait states. Table 295 lists the configuration and status registers in the BBus Bridge module. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
BBus Bridge Buffer Descriptor Pointer register Address: A040 0000 / 0020 This register contains a 32-bit pointer to the first buffer descriptor in a contiguous list of buffer descriptors. The BBus bridge contains a Buffer Descriptor Pointer register for each DMA channel; each register is 16 bytes in length.
BBus Bridge Control and Status registers Register bit assignment Bit(s) Access Mnemonic Reset Description D31 R/W CE 0 Channel enable Enables and disables DMA operations, as wanted. Write a 1 to this field after a DMA channel has entered the IDLE state for any reason, to initiate additional DMA transfers. D30 R/W CA 0 Channel abort When set, causes the current DMA operation to complete, then closes the buffer.
BBus Bridge Bit(s) Access Mnemonic Reset Description D24:23 R/W SB 0 Source burst 00 1 01 2 (Recommended for 8-bit devices) 10 4 (Recommended for 16-bit devices) 11 8 (Recommended for 32-bit devices) Defines the AHB maximum burst size allowed when reading from the source. D22:21 R/W DB 0 Destination burst 00 1 01 2 (Recommended for 8-bit devices) 10 4 (Recommended for 16-bit devices) 11 8 (Recommended for 32-bit devices) Defines the AHB maximum burst size when writing to the destination.
BBus Bridge Control and Status registers Bit(s) Access Mnemonic Reset Description D16 R/W RST 0 Reset Forces a reset of the DMA channel. Writing a 1 to this field forces all fields in the DMA Channel 1/2 Control register, except the INDEX field, to the reset state. The INDEX field is written with a value specified on signals ahb_wdat[9:0]. This field always reads back a 0. Writing a 1 to this field while the DMA channel is operational results in unpredictable behavior.
BBus Bridge Register bit assignment Bits Access Mnemonic Reset Description D31 RW1TC NCIP 0 Normal completion interrupt pending Set when a buffer descriptor has been closed. A normal DMA completion occurs when the BLEN count expires to 0 and the L bit in the Buffer descriptor is set, or when the peripheral device signals completion. D30 RW1TC ECIP 0 Error completion interrupt pending Set when the DMA channel finds either a bad buffer descriptor pointer or a bad data buffer pointer.
BBus Bridge Control and Status registers Bits Access Mnemonic Reset Description D27 RW1TC PCIP 0 Premature complete interrupt pending Set when a DMA transfer is terminated by assertion of the dma_done signal. NCIP is set when PCIP is set, for backward compatibility. D26:25 R/W Not used 0 Always set this field to 0. D24 R/W NCIE 0x0 Enable NCIP interrupt generation D23 R/W ECIE 0x0 Enable ECIP interrupt generation Always enable during normal operation.
BBus Bridge 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 POL Not used Not used 15 14 13 12 11 10 9 8 7 Not used SEL Register bit assignment Bits Access Mnemonic Reset Description D31:04 R/W Not used 0 Always set to 0. D03 R/W POL 0 Chip select polarity Defines the polarity of the memory interface chip select signal (stcsout[n]_n) connected to the external peripheral.
BBus Bridge Control and Status registers BBus Bridge Interrupt Status register Address: A040 1000 This register contains the interrupt status of the BBus peripherals. All interrupts must be serviced in the originating module.
BBus Bridge Bits Access Mnemonic Reset Description D01 R USB 0 USB module has asserted its interrupt. D00 R BBDMA 0 BBus DMA module has asserted its interrupt. Table 300: BBus Bridge Interrupt Status register BBus Bridge Interrupt Enable register Address: A040 1004 The BBus Bridge Interrupt Enable register allows you to enable or disable BBus interrupts on an individual basis as well as a global basis.
BBus Bridge Control and Status registers Bits Access Mnemonic Reset Description D23:13 R/W Not used 0x000 Always set this field to 0. D12 R/W Not used 0 Always write to 0. D11 R/W 1284E 0 Enable interrupt from IEEE-1284 module. D10 R/W I2CE 0 Enable interrupt from I2C module. D09 R/W SDTXE 0 Enable interrupt from SER transmit module D. D08 R/W SDRXE 0 Enable interrupt from SER receive module D. D07 R/W SCTXE 0 Enable interrupt from SER transmit module C.
BBus DMA Controller C H A P T E R 9 T he NS9750 ASIC BBus subsystem contains two DMA controllers, each with 16 channels. Note: These DMA controllers are different than the AHB DMA controllers discussed in the BBus Bridge chapter.
About the BBus DMA controllers About the BBus DMA controllers There are two BBus DMA controllers. One DMA controller supports all BBus peripherals except the USB device; the other DMA controller is dedicated to the USB device interface (see the USB Controller Module chapter for more information). Each DMA controller contains 16 channels, and each DMA channel moves data between external memory and internal peripherals in fly-by mode, minimizing CPU intervention.
BBus DMA Controller Figure 83 shows the BBus DMA controller block. DMA Channel Arbiter Channel Transfer Attributes DMA Control State Machine DMA Context RAM 128x32 BBUS Interface BBUS Figure 83: DMA controller block Each DMA controller arbiter determines in which channel the state machine currently is operating. DMA context memory Each DMA controller maintains state for all 16 channels using an on-chip SRAM known as the context memory. One 128x32 single port SRAM macrocell comprises this memory.
DMA buffer descriptor Offset Description 0x00 Buffer descriptor pointer 0x01 Control register 0x02 Status register 0x03 Unused 0x04 Source Address register 0x05 Buffer Length register 0x06 Destination Address register 0x07 Control flags and transfer status Table 302: DMA context memory entry DMA buffer descriptor All DMA channels operate using a buffer descriptor. Each DMA channel remains idle until enabled through the DMA Channel Control register.
BBus DMA Controller 31 30 29 28 16 OFFSET + 0 0 Source Address Reserved OFFSET + 4 Buffer Length Destination Address OFFSET + 8 OFFSET + C 15 W I L F Reserved Status Figure 84: DMA buffer descriptor Field Description Source address Identifies the starting location of the source data buffer. For transmit buffers. The source address can start on any byte boundary. For receive buffers. The source address must be word-aligned.
DMA buffer descriptor Field Description I The interrupt bit. When set, this bit tells the DMA controller to issue an interrupt to the CPU when the buffer is closed due to a normal channel completion. The interrupt occurs no matter what the normal completion interrupt enable configuration is for the DMA channel. L The last bit. This bit indicates end-of-packet status.
BBus DMA Controller Bits Mnemonic Description 15 MATCH1 Receive character match #1 14 MATCH2 Receive character match #2 13 MATCH3 Receive character match #3 12 MATCH4 Receive character match #4 11 BGAP Buffer gap timeout 10 CGAP Character gap timeout 09:04 UNUSED Not used — read back 0 03 RBRK Receive line break 02 RFE Receive frame error 01 RPE Receive parity error 00 ROVER Receive overrun error Table 304: Peripheral bit fields: Serial controller — UART RX mode Bits M
DMA buffer descriptor Bits Mnemonic Description 15:00 UNUSED Not used — read back 0 Table 307: Peripheral bit fields: Serial controller — SPI TX mode Bits Mnemonic Description 15:14 STATE 00 Undefined 01 Data phase transaction 10 Status phase transaction 11 No-data status phase transaction Defines the state of the endpoint after the most recent communication with the USB device module. This field is used primarily for debugging. 13 M31 See the USB Controller module chapter.
BBus DMA Controller DMA channel assignments Each BBus DMA controller contains 16 DMA channels. Controller DMA1 is dedicated to the BBus peripherals. Controller DMA2 is dedicated to the USB device endpoints. Any given DMA channel is hard-wired to a peripheral. Table 310 indicates which peripherals are hard-wired to which DMA channels, and the DMA mode (direction) required for each.
DMA Control and Status registers DMA Channel DMA channel peripheral Fly-by direction DMA2 1 USB device control-OUT endpoint #0 FBW DMA2 2 USB device control-IN endpoint #0 FBR DMA2 3 USB device endpoint#1 FBRW DMA2 4 USB device endpoint#2 FBRW DMA2 5 USB device endpoint#3 FBRW DMA2 6 USB device endpoint#4 FBRW DMA2 7 USB device endpoint#5 FBRW DMA2 8 USB device endpoint#6 FBRW DMA2 9 USB device endpoint#7 FBRW DMA2 10 USB device endpoint#8 FBRW DMA2 11 USB devi
BBus DMA Controller within each DMA module. The offsets allow address bits [08:05] to encode the DMA channel number.
DMA Control and Status registers Offset Description 9000 0130 / 9011 0130 DMA Channel 10 Control register 9000 0150 / 9011 0150 DMA Channel 11 Control register 9000 0170 / 9011 0170 DMA Channel 12 Control register 9000 0190 / 9011 0190 DMA Channel 13 Control register 9000 01B0 / 9011 01B0 DMA Channel 14 Control register 9000 01D0 / 9011 01D0 DMA Channel 15 Control register 9000 01F0 / 9011 01F0 DMA Channel 16 Control register 9000 0014 / 9011 0014 DMA Channel 1 Status/Interrupt Enable regi
BBus DMA Controller 9000 0000 / 0020 / 0040 / 0060 / 0080 / 00A0 / 00C0 / 00E0 / 0100 / 0120 / 0140 / 0160 / 0180 / 01A0 / 01C0 / 01E0 Address: DMA2 9011 0000 / 0020 / 0040 / 0060 / 0080 / 00A0 / 00C0 / 00E0 / 0100 / 0120 / 0140 / 0160 / 0180 / 01A0 / 01C0 / 01E0 The DMA Buffer Descriptor Pointer register contains a 32-bit pointer to the first buffer descriptor in a contiguous list of buffer descriptors. There is one Buffer Descriptor Pointer for each channel within each DMA controller module.
DMA Control and Status registers DMA Control register Address: DMA1 9000 0010 / 0030 / 0050 / 0070 / 0090 / 00B0 / 00D0 / 00F0 / 0110 / 0130 / 0150 / 0170 / 0190 / 01B0 / 01D0 / 01F0 Address: DMA2 9011 0010 / 0030 / 0050 / 0070 / 0090 / 00B0 / 00D0 / 00F0 / 0110 / 0130 / 0150 / 0170 / 0190 / 01B0 / 01D0 / 01F0 The DMA Control register contains required transfer control information. There is a DMA Control register for each channel within each DMA controller module.
BBus DMA Controller Bits Access Mnemonic Reset Description D27:26 R/W MODE 0 Fly-by mode 00 Fly-by write (peripheral-to-memory) 01 Fly-by read (memory-to-peripheral) 10 Undefined 11 Undefined Defines the fly-by transfer mode. D25:24 R/W BTE 0 Burst transfer enable 00 1 operand 01 2 operands 10 4 operands (Recommended) 11 Reserved Determines whether the DMA channel can use burst transfers through the bus. This configuration applies to both buffer descriptor and peripheral data access.
DMA Control and Status registers Bits Access Mnemonic Reset Description D15:10 R STATE 0 State field 0x00 Idle 0x20 Transfer in progress 0x18 Update buffer descriptor Describes the current state of the DMA controller state machine. D09:00 R INDEX 0 Index value Identifies the current byte offset pointer relative to the buffer descriptor pointer.
BBus DMA Controller Register bit assignment Bits Access Mnemonic Reset Description D31 RW1TC NCIP 0 Normal completion interrupt pending Set when a buffer descriptor is closed (for normal conditions). An interrupt is generated when either the NCIE (D24) bit is set or the IDONE (D18) bit is found active in the current buffer descriptor. A normal DMA channel completion occurs when the BLEN count (15:00) expires to 0 or when a peripheral device signals completion.
DMA Control and Status registers Bits Access Mnemonic Reset Description D28 RW1TC CAIP 0 Channel abort interrupt pending Set when the DMA channel finds the CA bit set in the DMA Channel Control register. An interrupt is generated when the CAIE (D21) bit is set. When CAIP Is set, the DMA channel retires the current buffer descriptor and stops until firmware writes a 1 to the CE bit (in the appropriate DMA Channel Control register).
BBus DMA Controller www.digiembedded.
BBus Utility C H A P T E R 1 0 T he BBus utility provides chip-level support for the low speed peripherals in the NS9750 ASIC that reside on the Digi proprietary BBus. The BBus utility handles functions such as bus monitors, GPIO control, and peripheral reset.
BBus Utility Control and Status registers BBus Utility Control and Status registers The BBus Utility configuration registers are located at base address 0x9060 0000. Table 315 lists the control and status registers in the BBus Utility. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
BBus Utility Master Reset register Address: 9060 0000 The Master Reset register contains the reset control signals for all BBus peripherals. All BBus peripherals, except the bridge, are held in reset after power-on reset is deasserted. All reset bits in this register are active high.
BBus Utility Control and Status registers GPIO Configuration registers GPIO Configuration registers #1 – #7 contain the configuration information for each of the 50 GPIO pins in the NS9750. Each GPIO pin is defined to have up to four functions. Configure each pin for the appropriate function and direction, as shown in Table 324: "GPIO Configuration register options" on page 528.
BBus Utility Bits Access Mnemonic Reset Description D31:28 R/W gpio47 0x3 gpio[47] configuration D27:24 R/W gpio46 0x3 gpio[46] configuration D23:20 R/W gpio45 0x3 gpio[45] configuration D19:16 R/W gpio44 0x3 gpio[44] configuration D15:12 R/W gpio43 0x3 gpio[43] configuration D11:08 R/W gpio42 0x3 gpio[42] configuration D07:04 R/W gpio41 0x3 gpio[41] configuration D03:00 R/W gpio40 0x3 gpio[40] configuration Table 318: GPIO Configuration Register #6 GPIO Config
BBus Utility Control and Status registers GPIO Configuration Register #4 Address: 9060 001C 31 30 29 28 27 26 gpio31 15 14 13 25 24 23 22 gpio30 12 11 10 gpio27 21 20 19 18 gpio29 9 8 7 6 16 gpio28 5 4 3 2 gpio25 gpio26 17 1 0 17 16 gpio24 Bits Access Mnemonic Reset Description D31:28 R/W gpio31 0x3 gpio[31] configuration D27:24 R/W gpio30 0x3 gpio[30] configuration D23:20 R/W gpio29 0x3 gpio[29] configuration D19:16 R/W gpio28 0x3 gpio[28]
BBus Utility Bits Access Mnemonic Reset Description D31:28 R/W gpio23 0x3 gpio[23] configuration D27:24 R/W gpio22 0x3 gpio[22] configuration D23:20 R/W gpio21 0x3 gpio[21] configuration D19:16 R/W gpio20 0x3 gpio[20] configuration D15:12 R/W gpio19 0x3 gpio[19] configuration D11:08 R/W gpio18 0x3 gpio[18] configuration D07:04 R/W gpio17 0x3 gpio[17] configuration D03:00 R/W gpio16 0x3 gpio[16] configuration Table 321: GPIO Configuration register #3 GPIO Config
BBus Utility Control and Status registers GPIO Configuration Register #1 Address: 9060 0010 31 30 29 28 27 26 gpio7 15 14 25 24 23 22 gpio6 13 12 11 10 gpio3 21 20 19 18 gpio5 9 8 7 6 16 1 0 gpio4 5 gpio1 gpio2 17 Bits Access Mnemonic Reset Description D31:28 R/W gpio7 0x3 gpio[7] configuration D27:24 R/W gpio6 0x3 gpio[6] configuration D23:20 R/W gpio5 0x3 gpio[5] configuration D19:16 R/W gpio4 0x3 gpio[4] configuration D15:12 R/W gpio3 0x3 g
BBus Utility Bits Access Mnemonic Description D01:00 R/W PINn 00 Function #0 01 Function #1 10 Function #2 11 Function #3 Use these bits to select the function to use. See the discussion of GPIO MUX for details about the available pin functions. Table 324: GPIO Configuration register options GPIO Control registers GPIO Control Registers #1 and #2 contain the control information for each of the 50 GPIO pins in the NS9750, as shown in Table 325 and Table 326.
BBus Utility Control and Status registers Bits Access Mnemonic Reset Description D15 R/W gpio47 0 gpio[47] control bit D14 R/W gpio46 0 gpio[46] control bit D13 R/W gpio45 0 gpio[45] control bit D12 R/W gpio44 0 gpio[44] control bit D11 R/W gpio43 0 gpio[43] control bit D10 R/W gpio42 0 gpio[42] control bit D09 R/W gpio41 0 gpio[41] control bit D08 R/W gpio40 0 gpio[40] control bit D07 R/W gpio39 0 gpio[39] control bit D06 R/W gpio38 0 gpio[38] control
BBus Utility Bits Access Mnemonic Reset Description D31 R/W gpio31 0 gpio[31] control bit D30 R/W gpio30 0 gpio[30] control bit D29 R/W gpio29 0 gpio[29] control bit D28 R/W gpio28 0 gpio[28] control bit D27 R/W gpio27 0 gpio[27] control bit D26 R/W gpio26 0 gpio[26] control bit D25 R/W gpio25 0 gpio[25] control bit D24 R/W gpio24 0 gpio[24] control bit D23 R/W gpio23 0 gpio[23] control bit D22 R/W gpio22 0 gpio[22] control bit D21 R/W gpio21 0 gpi
BBus Utility Control and Status registers Bits Access Mnemonic Reset Description D05 R/W gpio5 0 gpio[5] control bit D04 R/W gpio4 0 gpio[4] control bit D03 R/W gpio3 0 gpio[3] control bit D02 R/W gpio2 0 gpio[2] control bit D01 R/W gpio1 0 gpio[1] control bit D00 R/W gpio0 0 gpio[0] control bit Table 326: GPIO Control Register #1 GPIO Status registers GPIO Status Registers #1 and #2 contain the status information for each of the 50 GPIO pins in the NS9750, as shown in T
BBus Utility Bits Access Mnemonic Reset Description D16 R gpio48 undefined gpio[48] status bit D15 R gpio47 undefined gpio[47] status bit D14 R gpio46 undefined gpio[46] status bit D13 R gpio45 undefined gpio[45] status bit D12 R gpio44 undefined gpio[44] status bit D11 R gpio43 undefined gpio[43] status bit D10 R gpio42 undefined gpio[42] status bit D09 R gpio41 undefined gpio[41] status bit D08 R gpio40 undefined gpio[40] status bit D07 R gpio39 undefi
BBus Utility Control and Status registers Note: The reset values for all of the status bits are undefined because they depend on the state of the GPIO pins to NS9750.
BBus Utility Bits Access Mnemonic Reset Description D06 R gpio6 undefined gpio[6] status bit D05 R gpio5 undefined gpio[5] status bit D04 R gpio4 undefined gpio[4] status bit D03 R gpio3 undefined gpio[3] status bit D02 R gpio2 undefined gpio[2] status bit D01 R gpio1 undefined gpio[1] status bit D00 R gpio0 undefined gpio[0] status bit Table 328: GPIO Status Register #1 BBus Monitor register Address: 9060 0050 Write 0 to this register.
BBus Utility Control and Status registers BBus DMA Interrupt Status register Address: 9060 0060 The BBus DMA Interrupt Status register contains the interrupt status bits for the BBus DMA Controller. The interrupt bits are active high. Service these interrupts in the BBus DMA controller.
BBus Utility Bits Access Mnemonic Reset Description D02 R BINT3 0 BBus DMA channel #3 interrupt status D01 R BINT2 0 BBus DMA channel #2 interrupt status D00 R BINT1 0 BBus DMA channel #1 interrupt status Table 329: BBus DMA Interrupt Status register BBus DMA Interrupt Enable register Address: 9060 0064 The BBus DMA Interrupt Enable register allows you to enable or disable the BBus DMA interrupts on an individual basis. Writing a 1 enables the interrupt.
BBus Utility Control and Status registers Bits Access Mnemonic Reset Description D07 R/W BINT_EN8 0 BBus DMA channel #8 interrupt enable D06 R/W BINT_EN7 0 BBus DMA channel #7 interrupt enable D05 R/W BINT_EN6 0 BBus DMA channel #6 interrupt enable D04 R/W BINT_EN5 0 BBus DMA channel #5 interrupt enable D03 R/W BINT_EN4 0 BBus DMA channel #4 interrupt enable D02 R/W BINT_EN3 0 BBus DMA channel #3 interrupt enable D01 R/W BINT_EN2 0 BBus DMA channel #2 interrupt enable
BBus Utility Bits Access Mnemonic Reset Description D03 R/W OUTEN 0 Enables the USB output driver during USB loopback testing. The output driver is enabled only when either the host or device indicates that it is driving the USB pins. Writing a 1 enables this feature. D02 R/W SPEED 1 0 Low speed (1.5 Mbps) 1 Full speed (12 Mbps) Defines the operational speed of the USB device block.
BBus Utility Control and Status registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 I2C IEEE 1284 SerD SerC SerA SerB USB DMA Not used 15 14 13 Not used 12 11 10 AHBM 9 8 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:13 R Not used 0x0 Always read as 0x0 D12 R/W AHBM Reset to the value provided on strapping pin gpio[44] AHB bus master 0 Little endian 1 Big endian D11:08 N/A Reserved N/A N/A D0
BBus Utility Bits Access Mnemonic Reset Description D02 R/W SerB 0 Serial controller port B 0 Little endian 1 Big endian D01 R/W USB 0 USB 0 Little endian 1 Big endian This does not affect the USB DMA controller. D00 R/W DMA Reset to the value provided on strapping pin gpio[44] BBus DMA 0 Little endian 1 Big endian This field controls both the general BBus DMA controller and the USB DMA controller.
I2C Master/Slave Interface C H A P T E R 1 1 T he I2C master/slave interface provides an interface between the ARM CPU and the I2C bus. The I2C master/slave interface basically is a parallel-to-serial and serial-to-parallel converter. The parallel data received from the ARM CPU has to be converted to an appropriate serial form to be transmitted to an external component using the I2C bus.
Overview Overview The I2C module is designed to be a master and slave. The slave is active only when the module is being addressed during an I2C bus transfer; the master can arbitrate for and access the I2C bus only when the bus is free (idle) — therefore, the master and slave are mutually exclusive. Physical I 2 C bus The physical I2C bus consists of two open-drain signal lines: serial data (SDA) and serial clock (SCL).
I2C Master/Slave Interface I 2 C external addresses I2C external [bus] addresses are allocated as two groups of eight addresses (0000XXX and 1111XXX), as shown in Table 334.
I2C command interface Locked interrupt driven mode I2C operates in a locked interrupt driven mode, which means that each command issued must wait for an interrupt response before the next command can be issued (illustrated in "Flow charts," beginning on page 556). The first bit of the command — 0 or 1 — indicates to which module — master or slave, respectively — the command in the CMD field (of the CMD_TX_DATA_REG; see page 548) is sent.
I2C Master/Slave Interface Bus arbitration Any M_READ or M_WRITE command causes the I2C module to participate in the bus arbitration process when the I2C bus is free (idle). If the module becomes the new bus owner, the transaction goes through. If the module loses bus arbitration, an M_ARBIT_LOST interrupt is generated to the host processor and the command must be reissued. I 2 C registers All registers have 8-bit definitions, but must be accessed in pairs.
I2C registers Command Transmit Data register Address: 9050 0000 The Command Transmit Data (CMD_TX_DATA_REG) register is the primary interface register for transmission of data between the NS9750 BBus and I2C bus. This register is write only.
I2C Master/Slave Interface Status Receive Data register Address: 9050 0000 The Status Receive Data register (STATUS_RX_DATA_REG) is the primary interface register for receipt of data between the NS9750 BBus and I2C bus. This register is read only.
I2C registers Master Address register Address: 9050 0004 If using 7-bit addressing, the master device address field uses only bits D07:01; otherwise, all 10 bits are used. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 6 5 4 3 2 1 16 Reserved 15 14 13 12 11 10 9 8 7 Reserved Master device address 0 Mstr addr mode Register bit assignment Bits Access Mnemonic Reset Description D10:01 R/W MDA 00hex Master device address Used for selecting a slave.
I2C Master/Slave Interface Slave Address register Address: 9050 0008 If using 7-bit addressing, the slave device address field uses only bits D07:01; otherwise, bits 10:01 are used.
I2C registers Configuration register Address: 9050 000C The Configuration register controls the timing on the I2C bus. This register also controls the external interrupt indication, which can be disabled. The I2C bus clock timing is programmable by the scl_ref value (D08:00).
I2C Master/Slave Interface Bits Access Mnemonic Reset Description D14 R/W TMDE 1 Timing characteristics of serial data and serial clock 0 Standard mode 1 Fast mode D13 R/W VSCD 1 Virtual system clock divider for master and slave Must be set to 0. D12:09 R/W SFW Fhex Spike filter width A default value of 1 is recommended. Available values are 0–15.
Interrupt Codes Code Name Master/slave Description 2hex M_NO_ACK Master No acknowledge by slave 3hex M_TX_DATA Master TX data required in register TX_DATA 4hex M_RX_DATA Master RX data available in register RX_DATA 5hex M_CMD_ACK Master Command acknowledge interrupt 6hex N/A N/A Reserved 7hex N/A N/A Reserved 8hex S_RX_ABORT Slave The transaction is aborted by the master before the slave performs a NO_ACK.
I2C Master/Slave Interface Software driver The I2C master software driver uses three commands only: M_READ to start a read sequence M_WRITE M_STOP to start a write sequence to give up the I2C bus If, during a read or write sequence, another M_READ or M_WRITE is requested by the ARM CPU, a restart is performed on the I2C bus. This opens the opportunity to provide a new slave device address in the MAster Address register before the command request.
Flow charts Flow charts Master module (normal mode, 16-bit) host idle write cmd M_READ write cmd M_WRITE write TX_DATA_REG write (optional) M_ADDR_REG 1 wait irq read rx/status 4 M_ARBIT_LOST irq 2 wait irq read rx/status wait irq read status M_NO_ACK irq 4 write cmd M_STOP M_RX_DATA irq 3 wait irq read status write cmd M_NOP M_CMD_ACK irq write (optional) M_ADDR_REG 1 write cmd M_READ 556 write cmd M_WRITE NS9750 Hardware Reference write cmd M_STOP M_TX_DATA irq write cmd M_NOP w
I2C Master/Slave Interface Notes: 1 Writing M_ADDR_REQ is not required if the device address is not changed. 2 Read on a non-existing slave. 3 Do not wait for the slave to perform a NO_ACK. 4 STATUS_REG and RX_DATA_REG are read simultaneously.
LCD Controller C H A P T E R 1 2 T he NS9750 LCD (Liquid Crystal Display) controller is a DMA master module that connects to the AHB bus. The LCD controller provides the signals required to interface directly to TFT and STN color and monochrome LCD panels. LCD controller timing diagrams can be found in the Timing chapter.
LCD features LCD features The NS9750 LCD controller provides these features: Dual 64-deep, 32-bit wide FIFOs, for buffering incoming display data Support for color and monochrome single- and dual-panel for Super Twisted Nematic (STN) displays with 4- or 8-bit interfaces Support for Thin Film Transistor (TFT) color displays Resolution programmable up to 1024 x 768 15 gray-level mono, 3375 color STN, and 64K color TFT support – Patented gray-scale algorithm 1, 2, or 4 bits-per-pixel (bpp) palettized displ
LCD Controller Signal polarity, active high or low AC panel bias Panel clock frequency Bits-per-pixel Display type, STN mono/color or TFT STN 4- or 8-bit interface mode STN dual- or single-panel mode Little endian, big endian, or WinCE mode Interrupt generation event LCD panel resolution The LCD can be programmed to support a wide range of panel resolutions, including but not limited to: 320 x 200, 320 x 240 640 x 200, 640 x 240, 640 x 480 800 x 600 1024 x 768 LCD panel support The LCD controller support
LCD features Number of colors The number of colors supported differs per panel type. TFT panels TFT panels support one or more of these color modes: 1 bpp, palettized, 2 colors selected from available colors 2 bpp, palettized, 4 colors selected from available colors 4 bpp, palettized, 16 colors selected from available colors 8 bpp, palettized, 256 colors selected from available colors 16 bpp, direct 5:5:5 RGB, with one bpp usually not used.
LCD Controller Mono STN panels Mono STN panels support one or more of these modes: 1 bpp, palettized, 2 grayscales selected from 15 2 bpp, palettized, 4 grayscales selected from 15 4 bpp, palettized, 15 grayscales selected from 15 LCD power up and power down sequence support This procedure provides an example of how the LCD controller can be programmed to provide the powerup sequence to an LCD panel (see Figure 85, "Power up and power down sequences," on page 564): 1 VDD is applied simultaneously to the
LCD controller functional overview LCD on sequence LCD off sequence Min. (display specific) ms (provided through software) Min. 0ms Vdd LCD Configured LcdEn=0 CLLP, CLCP, CLFP CLAC, CLLE LcdEn=1 Vee LcdPwr=1 CLPOWER CLD[23:0] LcdPwr=0 Min. (display specific) ms (provided through software) Min.
LCD Controller Depending on the LCD type and mode, the unpacked data can represent one of the following: An actual true display gray or color value An address to a 256 x 16 bit wide palette RAM gray or color value With STN displays, either a value obtained from the addressed palette location or the true value is passed to the grayscaling generators.
LCD controller functional overview Signals and interrupts The LCD controller provides a set of programmable display control signals, and generates individual interrupts for different conditions.
LCD Controller Register/palette programming LCD panel control signals AHB slave interface Panel clock generator Timing controller LCD panel clock Palette RAM external Palette Upper half-word AHB master interface DMA FIFO controller Pixel serializer Greyscaler Lower half-word Frame buffer access Upper panel FIFO Bit 0 Lower panel FIFO Upper panel formatter TFT panel data TRUE COLOR LCD panel data Lower panel formatter TFT Figure 86: LCD controller block diagram www.digiembedded.
AHB interface AHB interface The AHB interface includes the AHB slave interface and the AHB master interface. AHB master and slave interfaces The AHB master interface transfers display data from memory to the LCD controller DMA FIFOs. The AHB slave interface connects the LCD to the AHB bus and provides CPU accesses to the registers and palette RAM.
LCD Controller Pixel serializer The pixel serializer block reads the 32-bit wide LCD data from DMA FIFO output port, and extracts 24, 16, 8, 4, 2, or 1 bpp, depending on the current mode of operation. The LCD controller supports big endian, little endian, and WinCE data formats. In dual panel mode, data is read alternately from the upper and lower DMA FIFOs.
AHB interface DMA FIFO OUTPUT BITS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 bpp 1 p31 p30 p15 2 1 0 3 p14 p13 p12 1 0 1 0 2 1 0 3 7 6 5 4 15 14 13 12 p10 1 0 1 0 2 1 0 3 3 2 1 0 11 10 9 8 p7 4 p11 p9 1 0 1 0 2 1 0 3 7 6 5 4 7 6 5 23 22 21 p6 1 0 2 1 0 3 2 1 0 4 3 2 1 0 20 19 18 17 16 p5 p4 p3 8 p8 p2 p1 16 p0 24 Figure 87:
LCD Controller DMA FIFO OUTPUT BITS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 bpp 1 p0 p1 p0 2 p1 1 0 3 2 p2 p3 1 0 1 0 1 0 3 2 p0 4 p4 p5 1 0 1 0 1 0 3 2 p1 p6 1 0 1 0 1 0 1 0 3 2 1 0 p2 p3 p0 8 p7 p1 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 p0 16 p0 24 Figure 89: BBBP, DMA FIF
AHB interface DMA FIFO OUTPUT BITS 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p26 p27 p28 p29 p30 p31 p16 p17 p18 p19 p20 p21 p22 p23 bpp 1 p24 2 p25 p12 1 0 3 7 p13 p14 p15 1 0 1 0 2 1 0 3 6 5 4 3 4 p8 p9 1 0 1 0 2 1 0 3 2 1 0 p6 p11 1 0 1 0 2 1 0 3 7 6 5 4 7 6 5 23 22 21 p7 8 p10 1 0 2 1 0 3 2 1 0 4 3 2 1 0 20 19 18 17 16 p4 p5 p3 p2 16 p1 15 14 13 12 11 10 9 8 24 p0 Figure 91:
LCD Controller RAM palette The palette RAM is a 256 x 16 bit dual port RAM, physically structured as 128 x 32 bit. This allows two entries to be written into the palette from a single word write access. The least significant bit of the serialized pixel data selects between upper and lower halves of the palette RAM. The half selected depends on the byte-ordering mode.
AHB interface In 16- and 24-bpp TFT mode, the palette is bypassed and the pixel serializer output is used as the TFT panel data. Grayscaler A unique grayscale algorithm drives mono and color STN panels. For mono displays, the algorithm provides 15 grayscales. For STN color displays, the three color components (red, green, and blue) are grayscaled simultaneously, resulting in 3375 (15 x 15 x 15) colors available.
LCD Controller Generating interrupts The LCD controller has three individually masked interrupts and a single combined interrupt. The single combined interrupt is asserted if any of the combined interrupts are asserted and unmasked. External pad interface signals The external pad interface signals are brought out through GPIO.
AHB interface Table 346 shows which CLD[23:0] pins provide the pixel data to the STN panel for each mode of operation.
LCD Controller Color STN single panel Color STN dual panel 4-bit mono STN single panel 4-bit mono STN dual panel 8-bit mono STN single panel 8-bit mono STN dual panel Ext pin GPIO pin & description CLD[7] AE8=LCD data bit 7 (O1) CUSTN[0]1 CUSTN[0]1 N/A N/A MUSTN[0] MUSTN[0]1 CLD[6] AD9=LCD data bit 6 (O1) CUSTN[1] CUSTN[1] N/A N/A MUSTN[1] MUSTN[1] CLD[5] AF8=LCD data bit 5 (O1) CUSTN[2] CUSTN[2] N/A N/A MUSTN[2] MUSTN[2] CLD[4] AE9=LCD data bit 4 (O1) CUSTN[3] CUSTN[3]
AHB interface External pin TFT 24 bit TFT 15 bit CLD[15] Green[7] Blue[2] CLD[14] Green[6] Blue[1] CLD[13] Green[5] Blue[0] CLD[12] Green[4] Intensity bit CLD[11] Green[3] Green[4] CLD[10] Green[2] Green[3] CLD[9] Green[1] Green[2] CLD[8] Green[0] Green[1] CLD[7] Red[7] Green[0] CLD[6] Red[6] Intensity bit CLD[5] Red[5] Red[4] CLD[4] Red[4] Red[3] CLD[3] Red[3] Red[2] CLD[2] Red[2] Red[1] CLD[1] Red[1] Red[0] CLD[0] Red[0] Intensity bit Table 347: LCD TFT
LCD Controller If you want reduced resolution, the least significant color bits can be dropped, starting with Red[0], Green[0], and Blue[0]. Registers Table 349 lists the LCD controller registers. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
Registers LCDTiming0 Address: A080 0000 The LCDTiming0 register controls the horizontal axis panel, which includes: Horizontal synchronization pulse width (HSW) Horizontal front porch (HFP) period Horizontal back porch (HBP) period Pixels-per-line (PPL) 31 30 29 28 27 26 25 24 23 22 21 20 HBP 15 14 13 12 19 18 17 16 3 2 1 0 HFP 11 10 9 8 7 6 HSW 5 4 PPL Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:24 R/W HBP 0x00 Horizontal back
LCD Controller Bits Access Mnemonic Reset Description D15:08 R/W HSW 0x00 Horizontal synchronization pulse width Width of the CLLP signal in CLCP periods. Program this field with value minus 1. HSW specifies the pulse width of the line clock in passive mode, or the horizontal synchronization pulse in active mode. D07:02 R/W PPL 0x00 Pixels-per-line Actual pixels-per-line = 16 * (PPL+1) The PPL field specifies the number of pixels in each line or row of the screen.
Registers LCDTiming1 Address: A080 0004 The LCDTiming1 register controls the vertical axis panel, which includes: Number of lines-per-panel (LPP) Vertical synchronization pulse width (VSW) Vertical front porch (VFP) period Vertical back porch (VBP period) 31 30 29 28 27 26 25 24 23 22 21 20 VBP 15 14 13 12 19 18 17 16 3 2 1 0 VFP 11 10 9 8 7 6 VSW 5 4 LPP Register bit assignment Bits Access Mnemonic Reset Description D31:24 R/W VBP 0x00 Vertical back porch Numb
LCD Controller Bits Access Mnemonic Reset Description D23:16 R/W VFP 0x00 Vertical front porch Number of inactive lines at the end of the frame, before vertical synchronization period. Program this field to zero on passive displays, to avoid reduced contrast. VFP specifies the number of blank lines to insert at the end of each frame. Once a complete frame of pixels is transmitted to the LCD display, the value in VFP counts the number of horizontal synchronization lines to wait.
Registers 31 30 29 28 27 26 25 24 23 22 21 BCD Reserved 15 14 13 12 11 Rsvd IOE IPC IHS IVS 10 20 19 18 17 16 4 3 2 1 0 CPL 9 8 7 6 ACB 5 Rsvd PCD Register bit assignment Bits Access Mnemonic Reset Description D31:27 N/A Reserved N/A N/A D26 R/W BCD 0x0 Bypass pixel clock divider Set this field to 1 to bypass the pixel clock divider logic. Used primarily for TFT displays.
LCD Controller Bits Access Mnemonic Reset Description D13 R/W IPC 0x0 Invert panel clock 0 Data changes on the rising edge of CLCP. 1 Data changes on the falling edge of CLCP Controls the phasing of the LCD data relative to the LCD clock (CLCP). The NS9750 changes the data on the opposite edge of the clock used to capture the data.
Registers Bits Access Mnemonic Reset Description D04:00 R/W PCD 0x00 Panel clock divisor Derives the LCD panel clock frequency CLCP from the CLCDCLK frequency: CLCP = CLCDCLK/(PCD+2) For mono STN displays with a 4- or 8-bit interface, the panel clock is a factor of four and eight down on the actual individual pixel clock rate. For color STN displays, 2 2/3 pixels are output per CLCP cycle, resulting in a panel clock of 0.375 times.
LCD Controller LCDTiming3 Address: A080 000C LCDTiming3 controls whether the line-end signal, CLLE, is enabled. When enabled, a positive pulse, four CLCDCLK periods wide, is output on CLLE after a programmable delay from the last pixel of each display line. If the line-end signal is disabled, it is held permanently low.
Registers LCDUPBASE is used for these displays: TFT Single panel STN Upper panel of dual panel STN LCDLPBASE is used for the lower panel of dual panel STN displays. Important: You must initialize LCDUPBASE (and LCDLPBASE for dual panels) before enabling the LCD controller. The base address value optionally can be changed mid-frame, to allow doublebuffered video displays to be created.
LCD Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 LCDLPBASE 15 14 13 12 11 10 9 8 7 LCDLPBASE Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:02 R/W LCDLPBASE 0x00000000 LCD lower panel base address Starting address of the lower panel frame data in memory; the address is word-aligned. D01:00 R/W Not used 0x0 Read as 0.
Registers Register bit assignment Bits Access Mnemonic Reset Description D31:05 N/A Reserved N/A N/A D04 R/W MBERRINTRENB 0x0 AHB master bus error interrupt enable. D03 R/W VCOMPINTRENB 0x0 Vertical compare interrupt enable. D02 R/W LNBUINTRENB 0x0 Next base update interrupt enable. D01:00 N/A Not used 0x0 Always write 0. Table 357: LCDINTRENABLE register LCDControl register Address: A080 001C The LCDControl register controls the mode in which the LCD controller operates.
LCD Controller Bits Access Mnemonic Reset Description D16 R/W WATERMARK 0x0 LCD DMA FIFO watermark level 0 LCD controller requests AHB bus when either of the DMA FIFOs have at least four empty locations. 1 LCD controller requests AHB bus when either of the DMA FIFOs have at least eight empty locations. (Use this setting for optimum bus bandwidth.
Registers Bits Access Mnemonic Reset Description D07 R/W LcdDual 0x0 LCD interface is dual panel STN 0 Single panel LCD is in use. 1 Dual panel LCD is in use. D06 R/W LcdMono8 0x0 Monochrome LCD has 8-bit interface 0 Mono LCD uses 4-bit interface. 1 Mono LCD uses 8-bit interface. Controls whether monochrome STN LCD uses a 4or 8-bit parallel interface. Program this bit to 0 for other modes. D05 R/W LcdTFT 0x0 LCD is TFT 0 LCD is STN display; use grayscaler.
LCD Controller LCDStatus register Address: A080 0020 The LCDStatus register provides raw interrupt status. On a read, the register returns three bits that can generate interrupts when set. On writes to the register, a bit value of 1 clears the interrupt corresponding to that bit. Writing a 0 has no effect. R/C indicates an access of read or clear.
Registers LCDInterrupt register Address: A080 0024 The LCDInterrupt register is a bit-by-bit logical AND of the LCDStatus register and the LCDINTRENABLE register. Interrupt lines correspond to each interrupt. A logical OR of all interrupts is provided to the system interrupt controller.
LCD Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 LCDUPCURR 15 14 13 12 11 10 9 8 7 LCDUPCURR Register bit assignment Bits Access Mnemonic Reset Description D31:00 R LCDUPCURR X LCD upper panel current address value.
Registers Each word location contains two palette entries, which means that 128 word locations are used for the palette. When configured for little endian byte ordering, bits [15:00] are the lowernumbered palette entry and bits [31:16] are the higher-numbered palette entry. When configured for big endian byte ordering, bits [31:16] are the lowernumbered palette entry and bits [15:00] are the higher-numbered palette entry.
LCD Controller Bits Access Mnemonic Reset Description D20:16 R/W R[4:0] N/A Red palette data For STN color displays, only the four most significant bits (04:01) are used. Used for monochrome displays. D15 R/W Int1 N/A Intensity bit Can be used as the least significant bit of the R, G, and B inputs to a 6:6:6 TFT display, doubling the number of colors to 64K, where each color has two different intensities.
Interrupts Interrupts The LCD controller drives a single interrupt back to the system, from four interrupt sources. Each of the three individual maskable interrupt sources is enabled or disabled by changing the mask bits in the LCDINTRENABLE register. The status of the individual interrupt sources can be read from the LCDStatus register. The interrupt sources are described next.
LCD Controller LBUINTR — Next base address update interrupt The LCD next base address update interrupt is asserted when either the LCDUPBASE or LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR incrementers (respectively). This tells the system that it is safe to update the LCDUPBASE or LCDLPBASE registers with new frame base addresses, if required. This interrupt can be cleared by writing a 1 to the LNBU bit in the LCDStatus register. www.digiembedded.
Interrupts 600 NS9750 Hardware Reference
Serial Control Module: UART C H A P T E R 1 3 T he NS9750 ASIC supports four independent universal asynchronous/synchronous receiver/transmitter channels. Each channel supports several modes, conditions, and formats.
Features Features Each channel supports these features: DMA transfers to and from system memory Independent programmable bit-rate generator High speed data transfer: 1.
Serial Control Module: UART Figure 93 shows the structure of the serial module. Transmit State Machine Receive State Machine Transmit Fifo Receive Fifo Bit Rate Generator Config Figure 93: Serial Module structure Bit-rate generator Each serial channel supports an independent programmable bit-rate generator. The bit-rate generator runs both the transmitter and receiver of a given channel (there is no split speed support).
UART mode Name Description X1_SYS_OSC/M The frequency of the external crystal oscillator divided by 2 or 4. The divisor is 2 when the PLLND field in the PLL Configuration register is at least 0x13, producing a nominal frequency of 14.7456 MHz. The divisor is 4 when PLLND is less than 0x13, producing a nominal frequency of 7.3728 MHz. See the System Control Module chapter for information about the PLL Configuration register. BCLK The clock source for all peripherals that are attached to the BBus.
Serial Control Module: UART receiver waits for the start bit. When it finds the high-to-low transition, the receiver counts 8 sample times and uses this point as the bit-center for all remaining bits in the UART frame. Each bit-time is 16 clock ticks apart. When the UART is not transmitting data, it transmits a continuous stream of ones — referred to as the IDLE condition. When data transmission begins, the transmitter sends the start bit and the receiver is enabled.
FIFO management When the system is configured to operate in little endian mode, the least significant bytes in the word written to the FIFO are transmitted first. For example, the long word 0x11223344 results in the character 0x44 being transmitted first, and 0x11 being transmitted last. Processor interrupts vs. DMA The transmit FIFO can be filled using processor interrupts or the DMA controller.
Serial Control Module: UART When the system is configured to operate in little endian mode, the least significant bytes in the word written to the FIFO are read first. For example, the long word 0x11223344 results in the character 0x44 being read first, and 0x11 being read last. When reading from the receive FIFO, the processor must perform a long word read operation. Each time a read cycle to the receive FIFO is performed, the receive FIFO advances to the next long word entry.
Serial port performance To facilitate an interrupt when either the RRDY or RBC status bits are active, the processor must set one or both of the corresponding interrupt enables in Serial Channel B/A/C/D Control Register A. Using the DMA controller When using DMA, the processor need not interface with any of the serial port registers for data flow; rather, the processor must interface with the DMA channel registers and the DMA buffer descriptor block.
Serial Control Module: UART Address Description 9020 0008 Channel B Status Register A 9020 000C Channel B Bit-Rate register 9020 0010 Channel B FIFO Data register 9020 0014 Channel B Receive Buffer Gap Timer 9020 0018 Channel B Receive Character Gap Timer 9020 001C Channel B Receive Match register 9020 0020 Channel B Receive Match Mask register 9020 0034 Channel B Flow Control register 9020 0038 Channel B Flow Control Force register 9020 0040 Channel A Control Register A 9020 0044 Ch
Serial port control and status registers The configuration registers for serial controller C are located at 0x9030_0000; the configuration registers for serial controller D are located at 0x9030_0040. Table 366 shows a single, two-channel address map for serial controllers C and D.
Serial Control Module: UART Serial Channel B/A/C/D Control Register A Address: 9020 0000 / 0040 9030 0000 / 0040 There are two Serial Channel B/A/C/D Control Registers A within each two-channel serial controller module.
Serial port control and status registers Bits Access Mnemonic Reset Description D28 R/W EPS 0 Even parity select 0 Odd parity 1 Even parity Determines whether the serial channel uses odd or even parity when calculating the parity bit in UART mode. When the STICKP field is set, EPS defines the static state for the parity bit. D27 R/W PE 0 Parity enable Enables/disables parity generation/checking for the UART transmitter and receiver. The transmitter generates proper parity.
Serial Control Module: UART Bits Access Mnemonic Reset Description D21 R/W RL 0 Remote loopback Provides a remote loopback feature. When RL is set to 1, the TXD transmit output is connected to the RXD receive input. The RL field immediately echoes receive data back as transmit data. This field is used primarily as a test vehicle for external data equipment. D20 R/W LL 0 Local loopback Provides an internal local loopback feature.
Serial port control and status registers Bits Access Mnemonic Reset Description D08 R/W ERXDMA 0 Enable receive DMA Enables the receiver to interact with a DMA channel. The channel is configured to operate in DMA mode when ERXDMA is set to 1. In DMA mode, the DMA controller empties the receive data FIFO and delivers the data to memory. The receive status information from Status Registers B and C are moved automatically to the receive DMA buffer descriptor.
Serial Control Module: UART 31 30 29 28 RDM 15 RTSTX 14 13 Not used 12 27 26 RBGT RCGT 11 10 25 24 23 22 21 8 Reserved 7 6 5 Not used 19 18 BIT ORDR MODE Not used 9 20 4 17 16 Not used 3 2 1 0 Reserved www.digiembedded.
Serial port control and status registers Register bit assignment Bits Access Mnemonic Reset Description D31:28 R/W RDM 0x0 Enable receive data match [31] RDM1 [30] RDM2 [29] RDM3 [28] RDM4 Enables the receive data match comparators. A receive data match comparison detection can be used to close the current receive buffer descriptor. The last byte in the current receive data buffer contains the match character. Each of these bits enables the respective byte found in the Receive Match register.
Serial Control Module: UART Bits Access Mnemonic Reset Description D19 R/W BITORDR 0 Bit ordering 0 Bits are processed LSB first, MSB last 1 Bits are processed MSB first, LSB last Controls the order in which bits are transmitted and received in the Serial Shift register. D18:16 R/W Not used 0 Must be written as 0. D15 R/W RTSTX 0 Enable active RTS only while transmitting Controls the RTS indicator.
Serial port control and status registers 31 30 29 28 Match 1 2 3 4 15 14 13 12 RBRK RFE RPE 27 26 BGAP CGAP 11 10 ROVER RRDY 25 24 23 21 Not used 9 RHALF RBC 8 7 RFS DCDI 20 RXFDB 6 RII 5 DSRI 4 CTSI 19 18 17 16 DCD RI DSR CTS 3 2 1 0 THALF Not used T EMPTY TRDY Bits Access Mnemonic Reset Description D31:28 R MATCH 0x0 Match bit [31] Match1 [30] Match2 [29] Match3 [28] Match4 Set when a match character in the Receive Match register is configur
Serial Control Module: UART Bits Access Mnemonic Reset Description D26 R CGAP 0 Character GAP timer Set when the enable receive character GAP timer is set in Serial Channel Control Register B (see "RCGT" on page 616) and the timeout value defined in the Receive Character GAP Timer register (see "Serial Channel B/A/ C/D Receive Character GAP Timer" on page 632) has expired. This bit indicates that the maximum allowed time has passed since the previous byte was placed into the receive data buffer.
Serial port control and status registers Bits Access Mnemonic Reset Description D17 R DSR 0 Data set ready 0 Inactive 1 Active Indicates the current state of the EIA data set ready signal. D16 R CTS 0 Clear to send 0 Inactive 1 Active Indicates the current state of the EIA clear-to-send signal. D15 R RBRK 0 Receive break condition Indicates that a receive break condition has been found. The receive data buffer is closed under this condition.
Serial Control Module: UART Bits Access Mnemonic Reset Description D12 R ROVER 0 Receive overrun Indicates that a receive overrun error condition has been found. An overrun condition indicates that the FIFO was full while data needed to be written by the receiver. When the FIFO is full, any new receive data is discarded; the contents of the FIFO prior to the overrun condition remain the same. The receive data buffer is closed under this condition.
Serial port control and status registers Bits Access Mnemonic Reset Description D10 R RHALF 0 Receive FIFO half full Indicates that the receive data FIFO contains at least 20 bytes (5 lines). RHALF typically is used only in interrupt-driven applications; this field is not used for DMA operation. The RHALF status condition can be programmed to generate an interrupt by setting the corresponding IE bit in Serial Channel Control Register A.
Serial Control Module: UART Bits Access Mnemonic Reset Description D05 R DSRI 0 Change in DSR Indicates a state change in the EIA data set ready signal. A 1 indicates that a state change has occurred. This field is asserted only when the corresponding IE bit — RIC field, D[05] — is set to 1 in Serial Channel Control Register A. D04 R CTSI 0 Change in CTS Indicates a state change in the EIA clear-to-send signal. A 1 indicates that a state change has occurred.
Serial port control and status registers Serial Channel B/A/C/D Bit-rate register Address: 9020 000C / 004C 9030 000C / 004C The Serial Channel B/A/C/D Bit-rate register contains the serial channel timing reference control bits and the data rate control bits.
Serial Control Module: UART Bits Access Mnemonic Reset Description D28 R/W TXSRC 0 Transmit clock source 0 Internal 1 External (input using GPIO pin) Controls the source of the transmitter clock. The transmitter clock can be provided by an internal source selected using the TICS field (see D16). As an alternative, the transmitter clock can be provided by an input on GPIO pins gpio[7], gpio[15], gpio[23], and gpio[27] for serial ports B, A, C, and D, respectively.
Serial port control and status registers Bits Access Mnemonic Reset Description D25:24 R/W CLKMUX 00 Bit-rate generator clock source Controls the bit-rate generator clock source. The bit-rate generator can be configured to use one of four clock sources: x1_sys_osc/M (see Table 364, “Bit-rate generation 00 clock sources,” on page 604 for more information). This is the recommended setting for standard UART baud rate generation.
Serial Control Module: UART Bits Access Mnemonic Reset Description D20:19 R/W TDCR 00 Transmit clock divide rate 00 Not valid for UART 01 8x clock mode 10 16x clock mode 11 32x clock mode Determines the divide ratio for the transmitter clock. D18:17 R/W RDCR 00 Receive clock divide rate 00 Not valid for UART 01 8x clock mode 10 16x clock mode 11 32x clock mode Determines the divide ratio for the receiver clock. D16 R/W Not used 0 Always write 0 to this field.
Serial port control and status registers N field Baud rate x8 UART mode x16 UART mode x32 UART mode 75 N/A 12287 6143 150 12287 6143 3071 300 6143 3071 1535 600 3071 1535 767 1200 1535 767 383 2400 767 383 191 4800 383 191 95 7200 255 127 63 9600 191 95 47 14400 127 63 31 19200 95 47 23 28800 63 31 15 38400 47 23 11 57600 31 15 7 115200 15 7 3 230400 7 3 1 460800 3 1 0 921600 1 0 N/A 1843200 0 N/A N/A Table 371: Bit-rate exampl
Serial Control Module: UART N field Baud rate x8 UART mode x16 UART mode x32 UART mode 150 6143 3071 1535 300 3071 1535 767 600 1535 767 383 1200 767 383 191 2400 383 191 95 4800 191 95 47 7200 127 63 31 9600 95 47 23 14400 63 31 15 19200 47 23 11 28800 31 15 7 38400 23 11 5 57600 15 7 3 115200 7 3 1 230400 3 1 0 460800 1 0 N/A 921600 0 N/A N/A 1843200 N/A N/A N/A Table 372: Bit-rate examples for X1_SYS_OSC/4 Serial Channel B/A/C/
Serial port control and status registers Reading from the receive register empties the receive FIFO. Data is available when the RRDY bit is set in Serial Channel Status Register A. The RXFDB field in Serial Channel Status Register A identifies how many bytes are available to be read. Reading the Serial Channel FIFO Data register automatically clears the RRDY bit in Serial Channel Status Register A.
Serial Control Module: UART Register bit assignment Bits Access Mnemonic Reset Description D31 R/W TRUN 0 Buffer GAP timer enable 0 Disables the timer 1 Enables the timer D30:16 R/W Not used 0x0000 Must be written as 0. D15:00 R/W BT 0x0000 Buffer GAP timer Defines the required value for the receive buffer GAP timer. BT is a function of the channel bit-rate and the receive buffer size.
Serial port control and status registers Serial Channel B/A/C/D Receive Character GAP Timer Address: 9020 0018 / 0058 9030 0018 / 0058 The receive character GAP timer closes out a receive serial data buffer due to a gap between characters. This timer is configured to provide an interval in the range of 0.27us to 0.28S. The timer is reset when a character is received. When the timer reaches its programmed threshold, the receive data buffer is closed.
Serial Control Module: UART Bits Access Mnemonic Reset Description D19:00 CT CT 0x00000 Character GAP timer Defines the required value for the receive character GAP timer.
Serial port control and status registers Serial Channel B/A/C/D Receive Match register Address: 9020 001C / 005C 9030 001C / 005C The Serial Channel B/A/C/D Receive Match register contains the four receive data match bytes used in UART mode.
Serial Control Module: UART Serial Channel B/A/C/D Receive Match MASK register Address: 9020 0020 / 0060 9030 0020 / 0060 The Serial Channel B/A/C/D Receive Match MASK register contains the four receive match mask bytes that specify which bits in the Receive Match Data register should not be included in the match comparison. To mask a bit in the match comparison function, place a 1 in the same bit position in this register.
Serial port control and status registers Serial Channel B/A/C/D Flow Control register Address: 9020 0034 / 0074 9030 0034 / 0074 The Serial Channel B/A/C/D Flow Control register allows you to define the flow control operation of the serial controller.
Serial Control Module: UART Bits Access Mnemonic Reset Description D05:04 R/W FLOW3 10 Flow control enable 00 Disabled 01 Disabled 10 Change field FLOW_STATE to XON upon match 11 Change field FLOW_STATE to XOFF upon match Allows you to define the flow control characteristics using fields RDMB3 (see "RDMB3" on page 634) and RMMB3 (see "RMMB3" on page 635).
Serial port control and status registers Serial Channel B/A/C/D Flow Control Force register Address: 9020 0038 / 0078 9030 0038 / 0078 The Serial Channel B/A/C/D Flow Control Force register allows you to override the normal flow of transmit data.
Serial Control Module: UART Bits Access Mnemonic Reset Description D16 R/W FORCE_EN 0 Force transmit Allows you to force the transmitter to send the character specified by the FORCE_CHAR (see D07:00) field. All user-specified rules, such as bit order, parity, and number of stop bits, are enforced. Write this field only when TX_IDLE is set to 1. Hardware clears this field once the character has been transmitted. Write a 1 to enable this feature. D15:08 R Not used 0x00 Always read as 0x00.
Serial port control and status registers 640 NS9750 Hardware Reference
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Serial Control Module: SPI C H A P T E R 1 4 T he NS9750 ASIC supports four independent universal asynchronous/synchronous receiver/transmitter channels. Each channel supports several modes, conditions, and formats.
Features Features Each channel supports these features: DMA transfers to and from system memory Independent programmable bit-rate generator High speed data transfer (synchronous) – SPI master: 8.33 Mbps – SPI slave: 6.25 Mbps 32-byte TX FIFO 32-Byte RX FIFO Figure 94 shows the structure of the serial module.
Serial Control Module: SPI Bit-rate generator Each serial channel supports an independent programmable bit-rate generator. The bit-rate generator runs both the transmitter and receiver of a given channel (there is no split speed support). You can configure the bit-rate generator to use external clock input or internal system timing as its timing reference. This allows for a wider range of possible bitrates. Table 380 describes all possible clock reference sources used by the bit-rate generator.
SPI mode SPI mode The NS9750 ASIC SPI controller provides these key features: Four-wire interface (DATA_OUT, DATA_IN, CLK, ENABLE) Master or slave configuration Programmable MSB/LSB formatting Programmable ENABLE polarity Programmable SPI mode (0, 1, 2, 3) The SPI controller provides a full-duplex, synchronous, character-oriented data channel between master and slave devices, using a four-wire interface (DATA_OUT, DATA_IN, CLK, ENABLE). The master interface operates in a broadcast mode.
Serial Control Module: SPI Serial channel B/A/C/D bit rate register settings Mode functionality SPI mode SPCPOL TXCINV RXCINV SPI CLK Idle SPI DATA_IN capture edge SPI DATA-OUT drive edge 0 1 0 0 Low Rising Falling 1 0 1 1 High Falling Rising 2 1 1 1 Low Falling Rising 3 0 0 0 High Rising Falling Table 381: SPI mode definitions FIFO management Data flow between a serial controller and memory occurs through the FIFO blocks within each serial controller module.
FIFO management Processor interrupts vs. DMA The transmit FIFO can be filled using processor interrupts or the DMA controller. Using processor interrupts The processor can write one long word (4 bytes) of data to the transmit FIFO when the TRDY field in Serial Channel B/A/C/D Status Register A (see "Serial Channel B/A/ C/D Status Register A," beginning on page 657) is active high.
Serial Control Module: SPI When reading from the receive FIFO, the processor must perform a long word read operation. Each time a read cycle to the receive FIFO is performed, the receive FIFO advances to the next long word entry. The processor cannot read individual bytes from the same FIFO long word entry. Processor interrupts vs. DMA The receive FIFO can be emptied using processor interrupts or the DMA controller.
Serial port performance Using the DMA controller When using DMA, the processor need not interface with any of the serial port registers for data flow; rather, the processor must interface with the DMA channel registers and the DMA buffer descriptor block. To facilitate use of transmit DMA, the ERXDMA field in Serial Channel B/A/C/D Control register A must be set active high. When ERXDMA is set active high, disable the serial receiver interrupts.
Serial Control Module: SPI Address Description 9020 0044 Channel A Control Register B 9020 0048 Channel A Status Register A 9020 004C Channel A Bit-Rate register 9020 0050 Channel A FIFO Data register Table 382: Serial channel B & A configuration registers The configuration registers for serial controller C are located at 0x9030_0000; the configuration registers for serial controller D are located at 0x9030_0040. Table 383 shows a single, two-channel address map for serial controllers C and D.
Serial port control and status registers Serial Channel B/A/C/D Control Register A Address: 9020 0000 / 0040 9030 0000 / 0040 There are two Serial Channel B/A/C/D Control Registers A within each two-channel serial controller module.
Serial Control Module: SPI Bits Access Mnemonic Reset Description D20 R/W LL 0 Local loopback Provides an internal local loopback feature. When LL is set to 1, the internal receive data stream is connected to the TXD output signal. LL connects the serial channel receiver directly to the serial channel transmitter. This field is used primarily as a test vehicle for the serial channel driver firmware. D19:12 R/W Not used 0 This field should be written to 0.
Serial port control and status registers Bits Access Mnemonic Reset Description D00 R/W ETXDMA 0 Enable transmit DMA Enables the transmitter to interact with a DMA channel. The channel is configured to operate in DMA mode when ETXDMA is set to 1. In DMA mode, the DMA controller loads the transmit data FIFO from memory. The transmit status information from Status Register C is moved automatically to the transmit DMA buffer descriptor. This bit is cleared to pause the transmitter.
Serial Control Module: SPI Serial Channel B/A/C/D Control Register B Address: 9020 0004 / 0044 9030 0004 / 0044 There are two Serial Channel B/A/C/D Control Registers B within each two-channel serial controller module. The CE field in Serial Channel Control register A should not be set until these control bits are stabilized.
Serial port control and status registers Bits Access Mnemonic Reset Description D21:20 R/W MODE 00 Serial channel mode 00 UART mode 01 Reserved 10 SPI master mode 11 SPI slave mode Configures the serial channel to operate in UART or SPI modes. The MODE field must be set before the CE bit in Serial Channel B/A/C/D Control Register A is set to 1.
Serial Control Module: SPI Serial Channel B/A/C/D Status Register A Address: 9020 0008 / 0048 9030 0008 / 0048 The fields in Serial Channel B/A/C/D Status Register A operate differently when DMA mode is used. Many fields are not required for DMA mode, as they are copied to the status field in the DMA buffer descriptor. See the discussion of the DMA Buffer Descriptor register status field in the BBus DMA Controller chapter.
Serial port control and status registers Bits Access Mnemonic Reset Description D12 R ROVER 0 Receive overrun Indicates that a receive overrun error condition has been found. An overrun condition indicates that the FIFO was full while data needed to be written by the receiver. When the FIFO is full, any new receive data is discarded; the contents of the FIFO prior to the overrun condition remain the same. The receive data buffer is closed under this condition.
Serial Control Module: SPI Bits Access Mnemonic Reset Description D10 R RHALF 0 Receive FIFO half full Indicates that the receive data FIFO contains at least 20 bytes (5 lines). RHALF typically is used only in interrupt-driven applications; this field is not used for DMA operation. The RHALF status condition can be programmed to generate an interrupt by setting the corresponding IE bit in Serial Channel Control Register A.
Serial port control and status registers Bits Access Mnemonic Reset Description D02 R THALF 0 Transmit FIFO half empty Indicates that the transmit data FIFO contains room for at least 16 bytes. THALF typically is used only in interruptdriven applications; this field is not used for DMA operation. The THALF status condition can be programmed to generate an interrupt by setting the corresponding IE bit in Serial Channel Control Register A.
Serial Control Module: SPI Register bit assignment Bits Access Mnemonic Reset Description D31 R/W EBIT 0 Bit-rate generator enable Enables the internal bit-rate generator when set to 1. D30 R/W TMODE 0 Timing mode Must be set to 1. Use the additional timing configuration provided by the TDCR and RDCR fields (D[20:19] and D[18:17] in this register) to configure the channel for 1x, 8x, 16x, or 32x mode.
Serial port control and status registers Bits Access Mnemonic Reset Description D26 R/W TXEXT 0 Drive transmit clock external 0 Disable 1 Enable Enables the transmitter clock to be driven on GPIO pins gpio[7], gpio[15], gpio[23], gpio[27] for serial ports B, A, C, and D, respectively. For SPI master mode, set to 1 to enable. For SPI slave mode, set to 0 to disable. D25:24 R/W CLKMUX 00 Bit-rate generator clock source Controls the bit-rate generator clock source.
Serial Control Module: SPI Bits Access Mnemonic Reset Description D22 R/W RXCINV 0 Receive clock invert Controls the relationship between receive clock and receive data: When set to 0, the receive data input is sampled at the rising edge transition of the receive clock. Use 0 for SPI modes 0 and 3. When set to 1, the receive data input is sampled at the falling edge transition of the receive clock. Use 1 for SPI modes 1 and 2.
Serial port control and status registers Bits Access Mnemonic Reset Description D18:17 R/W RDCR 00 Receive clock divide rate 00 1x clock mode (only NRZ or NRZI allowed) 01 8x clock mode 10 16x clock mode 11 32x clock mode Determines the divide ratio for the receiver clock. If the DPLL is not used, use the 1x clock mode value (00). When the DPLL is used in the application, selecting TDCR/RDCR is a function of the receiver encoding.
Serial Control Module: SPI Bits Access Mnemonic Reset Description D15 R/W RICS 0 Receive internal clock source 0 Receiver uses the bit-rate generator output for the clock. 1 Receiver uses the extracted clock provided by the DPLL. Defines the receive clock source when the RXSRC (D29) field is set to 0. There are two sources for internal clocks: the bit-rate generator (BRG) and the receiver digital phase lock loop (DPLL). The bit-rate generator uses a divider mechanism for clock generation.
Serial port control and status registers the Serial Channel FIFO Data register automatically clears the RRDY bit in Serial Channel Status Register A. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DATA 15 14 13 12 11 10 9 8 7 DATA Register bit assignment Bits Access Mnemonic Reset Description D31:00 R/W DATA 0x00000000 Serial channel FIFO data field.
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IEEE 1284 Peripheral Controller C H A P T E R 1 5 T he IEEE 1284 peripheral port supports compatibility mode, nibble mode, byte mode, and ECP mode of operations as a peripheral device. The IEEE 1284 port does not support EPP/mode daisy chain or multiplexer operations.
Requirements Requirements Two components are required to run the IEEE 1284 peripheral-to-host interface: Clock divider. Required to generate the 1284-port operating clock from the BBus clock. The operating range of the port clock typically is 100 KHz–2 MHz. The clock divider is set using the granularity counter (see "Granularity Count register" on page 702). External transceivers. The data flow direction control is provided using a GPIO pin under software control.
IEEE 1284 Peripheral Controller Note: Traffic direction in the IEEE 1284 is classified as either forward or reverse. The forward direction is equivalent to NS9750 receive. Similarly, the reverse direction is equivalent to NS9750 transmit. Compatibility mode Compatibility mode is the standard parallel port (SPP) forward transmission mode (from the host), also known as the Centronics mode.
Overview Nibble mode Nibble mode can send a byte of information to the host by sending two nibbles. This mode operates only in reverse mode. Figure 97 shows the timing relationship on the port interface. Figure 97: Nibble mode data transfer cycles Byte mode Byte mode sends information to the host over the data lines, at 8 bits per cycle. The peripheral sets the PtrClk bit high to acknowledge the host. Figure 98 shows the timing relationship on the port interface.
IEEE 1284 Peripheral Controller ECP mode ECP (extended capability port) mode provides a high performance bi-directional communication path between the host and the peripheral. The ECP protocol provides two cycle types in both the forward and reverse directions: data cycles and command cycles. Two types of command cycles are supported by the IEEE peripheral: run length count and channel address. The transfer direction is controlled by the host until a ReverseRequest signal is issued by the host.
Overview Figure 99: ECP mode forward transfer cycles X Host processing sequence example: 1 The host puts the data on the data lines and indicates a data cycle by setting HostAck high. 2 The host asserts HostClk low to indicate valid data. 3 The peripheral acknowledges the host by setting PeriphAck to high. 4 The host sets HostClk to high. This edge should be used to latch the data into the peripheral. 5 The peripheral sets PeriphAck low, indicating that it’s ready for the next data byte.
IEEE 1284 Peripheral Controller Figure 100: ECP reverse channel transfer cycles Data and command FIFOs Separate data and command FIFOs are provided in the forward direction, and a single FIFO is provided in the reverse direction. These FIFOs can be accessed either through the appropriate DMA channel (see Table 310: "DMA channel assignments" on page 509) or directly by the CPU using access registers provided in this 1284 interface.
Overview Because the NS9750 functions only as a slave, it is not necessary to provide the capability of driving any non-IEEE 1284 compliant commands back to the host. Important: The 1284 commands are not designed to be stored and passed along. To store a non-IEEE 1284 command in the forward command FIFO, send an RLE command of count one (0x0), followed by the command you want to send.
IEEE 1284 Peripheral Controller Extensibility byte Definition Description 0011 0100 Request device ID using ECP mode with RLE Receive device ID with ECP data compression. 0000 0010 Reserved Reserved 0000 0001 Byte mode reverse channel transfer 0000 0000 Nibble mode reverse channel transfer Table 389: Extensibility byte values The NS9750 directly supports RLE compression. The device ID can be returned in any supported reverse channel mode.
BBus slave and DMA interface Address Register Description 9040 0008 FIFO Status FIFO Status register 9040 000C FwdCmdFifoReadReg Forward Command FIFO Read register 9040 0010 FwDatFifoReadReg Forward Data FIFO Read register 9040 0014 – 9040 0018 Reserved 9040 001C RvFifoWriteReg Reverse FIFO Write register 9040 0020 RvFifoWriteReg - Last Reverse FIFO Write Register - Last 9040 0024 FwdCmdDmaControl Forward Command DMA Control register 9040 0028 FwDatDmaControl Forward Data DMA Contr
IEEE 1284 Peripheral Controller Address Register Description 9040 016C – 9040 0170 Reserved 9040 0174 eca Forward Address register 9040 0178 pha Core Phase register Table 390: 1284 Control and Status registers IEEE 1284 General Configuration register Address: 9040 0000 The IEEE 1284 General Configuration register contains miscellaneous control settings for the IEEE 1284 module.
BBus slave and DMA interface Bits Access Mnemonic Reset Description D13 R/W CPS 0x0 Connector PLH signal 0 Indicates to the host that this interface is not ready to operate as an IEEE 1284 slave. 1 Indicates to the host that this interface is ready to operate as an IEEE 1284 slave. This bit should be set by software when the initialization of the 1284 interface is complete.
IEEE 1284 Peripheral Controller Bits Access Mnemonic Reset Description D00 R/W RM 0x0 Reverse mode (RevMode) 0 Direct CPU access 1 DMA control Table 391: IEEE 1284 General Configuration register Interrupt Status and Control register Address: 9040 0004 The Interrupt Status and Control register contains miscellaneous control settings for the IEEE 1284 module.
BBus slave and DMA interface Bits Access Mnemonic Reset Description D23 R/W FDBGM 0x0 Forward data FIFO byte gap mask (FwDatFifoByteGapMask) 0 Mask the interrupt 1 Enable the interrupt D22 R/W FCBGM 0x0 Forward command FIFO byte gap mask (FwCmdFifoByteGapMask) 0 Mask the interrupt 1 Enable the interrupt D21 R/W FDMBM 0x0 Forward data FIFO max buffer mask (FwDatFifoMaxBufMask) 0 Mask the interrupt 1 Enable the interrupt D20 R/W FCMBM 0x0 Forward command FIFO max buffer mask (FwCmdFif
IEEE 1284 Peripheral Controller Bits Access Mnemonic Reset Description D07 R/C FDFBG 0x0 Forward data FIFO byte gap (FwDatFifoByteGap) The forward data byte gap timer expired and the buffer closed. Set to 1 to clear this bit. D06 R/C FCFBG 0x0 Forward command FIFO byte gap (FwCmdFifoByteGap) The forward command byte gap timer expired and the buffer closed. Set to 1 to clear this bit.
BBus slave and DMA interface FIFO Status register Address: 9040 0008 The FIFO Status register allows the CPU to determine that status of all FIFOs in the 1284 module. You can ignore this register when running the 1284 interface in DMA mode.
IEEE 1284 Peripheral Controller Bits Access Mnemonic Reset Description D11 R FCFR 0x0 Forward command FIFO ready (FwCmdFifoReady) Asserted if forward command in FIFO is enabled to move data. Determined by FwCmdReadyThreshold (in the IEEE 1284 General Configuration register).
BBus slave and DMA interface Bits Access Mnemonic Reset Description D01 R RFAF 0x0 Reverse FIFO almost full (RvFifoAlmostFull) 0 FIFO can take more than 1–4 bytes 1 FIFO can take only one 1–4 byte entry This field is not valid id the FIFO is full. D00 R RFR 0x0 Reverse FIFO ready (RvFifoReady) Asserted if reverse data out FIFO is enabled to move data. Determined by RvDatReadyThreshold (in the IEEE 1284 General Configuration register).
IEEE 1284 Peripheral Controller Forward Data FIFO Read register Address: 9040 0010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 FwDatFifoReadReg 15 14 13 12 11 10 9 8 7 FwDatFifoReadReg Register bit assignment Bits Access Mnemonic Reset Description D31:00 R FwDatFifoReadReg N/A Reads up to four bytes from the Forward Data FIFO when in CPU mode.
BBus slave and DMA interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 RvFifoWriteReg - Last 15 14 13 12 11 10 9 8 7 6 RvFifoWriteReg - Last Register bit assignment Bits Access Mnemonic Reset Description D31:00 W RvFifoWriteReg N/A D31:00 W RvFifoWrite Reg — Last N/A Write one to four bytes to the Reverse FIFO when in CPU mode. A FIFO entry containing one byte or two bytes is written to Reverse FIFO Write Register — Last.
IEEE 1284 Peripheral Controller Forward Command DMA Control register Address: 9040 0024 The Forward Command DMA Control register controls when the Forward command DMA buffer is closed, using two components: 16-bit maximum buffer counter. The maximum buffer counter increments each time a DMA transfer occurs, by the number of bytes in the transfer. The counter is reset each time a DMA is completed.
BBus slave and DMA interface Register bit assignment Bits Access Mnemonic Reset Description D31:16 R/W FwCmdMaxBufSize 0x0 Forward command maximum buffer size Maximum buffer size in bytes. D15:00 R/W FwCmdByteGapTimer 0x0 Forward command byte gap timeout 16-bit byte gap timer in BBus clock cycles.
IEEE 1284 Peripheral Controller b Forward data FIFO ready, which normally means the threshold has been met, is asserted. This results in continuation of the currently active DMA until the FIFO is empty. c When the data in the FIFO, including the incomplete dwords in Step 1, is output through DMA, the DMA is terminated.
BBus slave and DMA interface Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R pd N/A Printer data pins Allows the CPU to read the status of the 8-bit data bus directly.
IEEE 1284 Peripheral Controller Port Control register Address: 9040 0108 The Port Control register can control IEEE 1284 pins only if no modes are enabled in the Master Enable register (see"Master Enable register" on page 697).
BBus slave and DMA interface Port Status register, peripheral Address: 9040 010C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 PERR SEL N_FLT Reserved 15 14 13 12 11 10 9 8 BUSY N_ACK Reserved Reserved Bits Access Mnemonic Reset Description D31:08 R Reserved 0x0 N/A D07 R BUSY 0x0 D06 R N_ACK 0x0 D05 R PERR 0x0 Allows the CPU to read the status of the peripheral control pins directly.
IEEE 1284 Peripheral Controller Register bit assignment Bits Access Mnemonic Reset Description D31:01 N/A Reserved N/A N/A D00 R/W PPtEn 0x0 Printer port enable 0 Force IEEE 1284 outputs to high impedance 1 Enable normal operation, depending on mode Table 403: fea — Feature Control Register A Feature Control Register B Address: 9040 0118 You must set bit[0] to 1 in Feature Control Register B. Bits[31:01] are reserved.
BBus slave and DMA interface Bits Access Mnemonic Reset Description D05 R/W PinSelectInterrupt 0x0 Pin select interrupt enable 0 Disable 1 Enable D04 R/W ECPChannel Address 0x0 Channel address update detect interrupt enable 0 Disable 1 Enable D03:02 N/A Reserved N/A N/A D01 R/W NegotiationStart 0x0 Negotiation start interrupt enable 0 Disable 1 Enable This interrupt is triggered when the rising edge of SELECTIN is found while in compatibility mode.
IEEE 1284 Peripheral Controller Master Enable register Address: 9040 0120 The Master Enable register enables different IEEE 1284 modes and automatic transfer modes. Set both AutoTransfer and AutoNegotiate to enable hardware to control the 1284 peripheral interface signals.
BBus slave and DMA interface Extensibility Byte Requested by Host Address: 9040 0124 This register is updated shortly after a new negotiation occurs (event 4 of the negotiation process; see the IEEE 1284 standard for more information).
IEEE 1284 Peripheral Controller Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07 N/A Not used 0x0 Set to 1. D06 R/W Enable reverse data transfers 0x0 0 1 D05:00 N/A Reserved N/A N/A Disable Enable Table 407: ecr — Extended Control register Interrupt Status register Address: 9040 012C Interrupts are cleared when this register is read. These interrupts are needed by software no matter which mode (DMA or CPU) is being used.
BBus slave and DMA interface Bits Access Mnemonic Reset Description D00 R TSDI 0x0 Transfer start detect interrupt Table 408: sti — Interrupt Status register Pin Interrupt Mask register Address: 9040 0134 The Pin Interrupt Mask register enables IEEE 1284 pin interrupts.
IEEE 1284 Peripheral Controller Pin Interrupt Control register Address: 9040 0138 The Pin Interrupt Control register configures IEEE 1284 pin interrupt edge levels.
BBus slave and DMA interface Granularity Count register Address: 9040 0168 The Granularity Count register controls the value of the granularity counter for automatic processing modes. According to the IEEE 1284 standards spec, the peripheral has a Tp (500ns) minimum setup pulse width for some signals. If, for example, the BBus is set to run at 50 MHz (20ns clock period), the Granularity Count register should be set to 25 (0x19) [500ns / 20ns].
IEEE 1284 Peripheral Controller Forward Address register Address: 9040 0174 The Forward Address register is updated when a channel address command is received during a forward ECP transfer. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 eca Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:08 R Reserved 0 N/A D07:00 R eca 0 Forward address.
BBus slave and DMA interface Core Phase (IEEE1284) register Address: 9040 0178 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 7 pha Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:08 R Reserved 0x0 N/A D07:00 R pha 0x0 0x00spp forward idle 0x01 spp forward data transfer 0x0f spp reset 0x14 negotiate phase 0x18 terminate phase 0x24 nibble/byte reverse idle 0x26 nibble/byte reverse data
IEEE 1284 Peripheral Controller Warning: The NS9750 cannot proceed to the Host Busy Data Available protocol state directly from negotiation state. If the host software supports the 1284 protocol reverse idle and interrupt host states (events 7, 18 – 20), the impact is a one-time loss of approximately 2,000ns at the beginning of data transfer. If the host does not support these states, however, the NS9750 will be unable to transmit data in nibble or byte mode.
USB Controller Module C H A P T E R 1 6 U SB 2.0 provides a standard “plug-and-play” interface for desktop communications at low to moderate speeds. The USB module in NS9750 supports both full-speed (12Mbps) and low-speed (1.5 Mbps) operation.
Overview Overview USB consists of point-to-point connections between one host and any number of hubs and devices; the number of hubs and devices combined cannot exceed 127.
USB Controller Module BBus Config DMA FIFOs and DMA channels Host block Device block XCVR Figure 101: USB module architecture The device block handles most packets that contain control and/or configuration information requiring device driver interaction to maintain only the DMA descriptor lists. The device block provides the appropriate handshake responses to USB.
USB device block given pipe has not been configured or updated, or otherwise is not ready to send or receive the required data, the device block issues NAKs to the USB. The host block supports the Open Host Controller Interface (OHCI) interface model for USB communications. The host block provides the registers and BBus mastering capability to traverse transaction lists in system memory per the OHCI interface, as well as transferring the in/out data to and from system memory.
USB Controller Module Packet and data flow The device block responds to packets initiated by the host. There are 16 DMA channels in this block. DMA channels 1 and 2 move data to and from system memory for control transfers for logical endpoint 0. DMA channels 3 through 13 move data for logical endpoints 1 through 11, respectively. DMA channels 14 through 16 are not used in the USB module. Data for each logical endpoint travels through a four-word FIFO.
Host block Logical and physical endpoints Each alternate of each interface of each configuration can use as many as 16 logical endpoints. Physical endpoints in the device block are programmable by software for configuration/interface/alternate number. type, direction, and MaxPacketSize. A physical endpoint, then, functions as one logical endpoint in one alternate of one interface of one configuration.
USB Controller Module To XCVR From XCVR OHCI Regs Slave IF text SIE FIFO Master IF FIFO BBUS Figure 103: USB host architecture Packet data flow The host block initiates all transfers on the USB. Data travels through a four-word FIFO in either direction. The Serial Interface Engine (SIE) performs the tasks required to receive and send packets on the USB. The host block is the master of the USB.
USB device endpoint consumed. Burst transfers move a maximum of 8 bytes in long word transactions. FIFO content from more than one transfer descriptor is broken into separate memory operations. USB device endpoint Any USB device requires a bidirectional control endpoint located at endpoint #0. The data FIFOs in the USB device application logic are unidirectional, so two data FIFOs are used to create a single bidirectional endpoint.
USB Controller Module Handling USB-IN packet errors USB-IN packet errors are sent from the USB device to the USB host. The USB host either responds with an ACK packet to indicate successful transmission or does not respond at all to indicate that there was an error in transmission. These are the steps that must be taken to retransmit the packet in error: 1 Determine that the error has occurred through an interrupt. The hardware places the endpoint FIFO into reset state and flushes the contents.
USB block registers USB block registers The USB module configuration registers are located at base address 9010_0000. Table 415 provides the address register map for the USB “modules” within the USB block. All configuration registers must be accessed as 32-bit words and as single accesses only. Bursting is not allowed.
USB Controller Module Global Control and Status register Address: 9010 0000 The Global Control and Status register contains all USB global and status information. The USB can operate as a device or host, but cannot operate as both simultaneously unless used in feedback mode. Feedback mode is useful for development and testing only. The inactive block (host or device) is held in reset.
USB Global registers Bits Access Mnemonic Reset Description D05 R SUSP 0 Suspend 0 The USB device is not in a suspended state 1 The USB device is in a suspended state Indicates whether the USB device is in a suspended state. D04:03 N/A Not used 0 Always write a 0. D02 R/W WKUP 0 Wakeup Value depends on the value written to the HST_DEV field (bit 0 in this register). When the NS9750 is in device mode, the device driver can write a 1 to this field to enable remote wakeup.
USB Controller Module Register bit assignment Bits Access Mnemonic Reset Description D31 R/W RESUME (RSME) 0 Resume Set to 1 by the device driver to initiate a resume sequence. This field is cleared to a 0 to end a resume sequence. D30 N/A Not used 0 Always read as 0. D29 R/W SPWR 0 Self-powered (SELF_PWR) This field should always be written as 1, since the NS9750 is always self-powered. D28 N/A Not used 0 Always write to 1.
USB Global registers Global Interrupt Enable register Address: 9010 000C The Global Interrupt Enable register contains the global interrupt enable information. All interrupts are enabled by writing a 1 and disabled by writing a 0.
USB Controller Module Bits Access Mnemonic Reset Description D17 R/W DMA4 0 DMA channel 4 interrupt D16 R/W DMA3 0 DMA channel 3 interrupt D15 R/W DMA2 0 DMA channel 2 interrupt D14 R/W DMA1 0 DMA channel 1 interrupt D13 R/W Not used 0 Always write to 0. D12 R/W FIFO 0 Generate an interrupt when any FIFO interrupt Status field is set and the corresponding interrupt is enabled using the FIFO Interrupt Enable register.
USB Global registers For diagnostics, each bit serviced here can also be set to 1 by writing a 1 when the bit is set to 0. The DMA interrupts must be serviced in the USB DMA device block. The FIFO interrupts must be serviced in the FIFO Interrupt Status register.
USB Controller Module Bits Access Mnemonic Reset Description D19 R DMA6 0 DMA channel 6 interrupt. Service in the USB DMA block. D18 R DMA5 0 DMA channel 5 interrupt. Service in the USB DMA block. D17 R DMA4 0 DMA channel 4 interrupt. Service in the USB DMA block. D16 R DMA3 0 DMA channel 3 interrupt. Service in the USB DMA block. D15 R DMA2 0 DMA channel 2 interrupt. Service in the USB DMA block. D14 R DMA1 0 DMA channel 1 interrupt. Service in the USB DMA block.
USB Global registers Bits Access Mnemonic Reset Description D01 RW1TC OHCI_IRQ 0 OHCI_IRQ Asserted when the USB is configured for host operation and the OHCI asserts an interrupt. D00 N/A Reserved N/A N/A Table 420: Global Interrupt Status register Device IP Programming Control/Status register Address: 9010 0014 The Device IP Programming Control/Status register contains the USB device CSR dynamic programming control and status information.
USB Controller Module Bits Access Mnemonic Reset Description D00 R/W CSRPRG 0 CSR dynamic programming support Enables dynamic programming support in the USB device IP. Program this field on powerup, then leave it unchanged. Write a 1 to enable this feature. Table 421: Device IP Programming Control/Status register USB host block registers The USB Host Block registers are for the host controller defined in the Open HCI specification for USB.
USB host block registers Address Register 9010 1008 HcCommandStatus register 9010 100C HcInterrupt Status register 9010 1010 HcInterruptEnable register 9010 1014 HcInterruptDisable register 9010 1018 HcHCCA (Host Controller Communications Area) register 9010 101C HcPeriodCurrentED (Endpoint Descriptor) register 9010 1020 HcControlHeadED register 9010 1024 HcControlCurrentED register 9010 1028 HcBulkHeadED register 9010 102C HcBulkCurrentED register 9010 1030 HcDoneHead register 9010
USB Controller Module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Reserved 15 14 13 12 11 10 9 8 Reserved REV Register bit assignment Bits Access Mnemonic Reset Description D31:08 N/A Reserved N/A N/A D07:00 R REV 10h Version of the OHCI specification being used. Table 423: HcRevision register HcControl register Address: 9010 1004 The HcControl register defines the operating modes for the host controller.
USB host block registers Bits Access Mnemonic Reset Description D10 R/W RWE 0b RemoteWakeupEnable Enables or disables the remote wakeup feature when upstream resume signaling is found. When this bit is set and the ResumeDetected bit in the HcInterruptStatus register is set, a remote wakeup is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupts.
USB Controller Module Bits Access Mnemonic Reset Description D07:06 R/W HCFS 00b HostControllerFunctionalState (b = binary) 00b USBRESET (initial state) 01b USBRESUME 10b USBOPERATIONAL 11b USBSUSPEND A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later. The host controller driver can determine whether the host controller has begun sending SOFs by reading the StartofFrame field of the HcInterruptStatus register.
USB host block registers Bits Access Mnemonic Reset Description D03 R/W IE 0b IsochronousEnable Enables/disables processing of the isochronous EDs. While processing the periodic list in a frame, the host controller checks the status of this bit when it finds an isochronous ED (F=1). If set (enabled), the host controller continues processing the EDs.
USB Controller Module The host controller uses the HcCommandStatus register to receive commands issued by the host controller driver, as well as to reflect the current status of the host controller. The HcCommandStatus register appears to the host controller driver as a write to set register. The host controller must ensure that bits written as 1 become set in the register while bits written as 0 remain unchanged in the register.
USB host block registers Bits Access Mnemonic Reset Description D15:04 N/A Reserved N/A N/A D03 R/W OCR 0b OwnershipChangeRequest Set by an OS host controller to request a change of control for the host controller. When set, the host controller sets the OwnershipChange field in the HcInterruptStatus register (see "HcInterruptStatus register," beginning on page 733). After the change is made, the OCR bit is cleared and remains so until the next request from OS host controller.
USB Controller Module Bits Access Mnemonic Reset Description D00 R/W HCR 0b HostControllerReset Set by the host controller driver to initiate a software reset of the host controller. Regardless of the functional state of the host controller, it moves to USBSUSPEND state. This bit is cleared by the host controller on completion of the reset operation.
USB host block registers Register bit assignment Bits Access Mnemonic Reset Description D31 N/A Reserved N/A N/A D30 R/W OC 0b OwnershipChange Set by the host controller when the host controller driver sets the OwnershipChangeRequest field in the HcCommandStatus register (see "HcCommandStatus register," beginning on page 730). This event, when unmasked, always generates a system management interrupt (SMI) immediately. This bit is tied to 0b when the SMI pin is not implemented.
USB Controller Module Bits Access Mnemonic Reset Description D02 R/W SF 0b StartofFrame Set by the host controller at each start of a frame and after the update of HccaFrameNumber. The host controller generates a SOF token at the same time. D01 R/W WDH 0b WritebackDoneHead Set immediately after the host controller has written HcDoneHead (see "HcDoneHead register," beginning on page 746) to HccaDoneHead.
USB host block registers 31 30 MIE OC 15 14 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RHSC FNO UE RD SF WDH SO Reserved 13 12 11 10 9 8 7 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31 R/W MIE 0b Master interrupt enable 0 Ignored by the host controller 1 Enables interrupt generation due to events specified in the other bits of this register.
USB Controller Module Bits Access Mnemonic Reset Description D02 R/W SF 0b Start of frame 0 Ignore 1 Enable interrupt generation due to start of frame. D01 R/W WDH 0b HcDoneHead writeback 0 Ignore 1 Enable interrupt generation due to HcDoneHead writeback. D00 R/W SO 0b Scheduling overrun 0 Ignore 1 Enable interrupt generation due to scheduling overrun.
USB host block registers Register bit assignment Bits Access Mnemonic Reset Description D31 R/W MIE 0b Master interrupt enable 0 Ignored by the host controller. 1 Disables interrupt generation due to events specified in other bits in this register. This field is set after a hardware or software reset. D30 R/W OC 0b Ownership change 0 Ignore 1 Disable interrupt generation due to ownership change.
USB Controller Module Bits Access Mnemonic Reset Description D00 R/W SO 0b Scheduling overrun 0 Ignore 1 Disable interrupt generation due to scheduling overrun. Table 428: HcInterruptDisable register HcHCCA register Address: 9010 1018 The HcHCCA register contains the physical address of the host controller communication area (HCCA), which is a RAM area with a defined format.
USB host block registers HcPeriodCurrentED register Address: 9010 101C The HcPeriodCurrentED register contains the physical address of the current isochronous or interrupt endpoint descriptor.
USB Controller Module Register bit assignment Bits Access Mnemonic Reset Description D31:04 R PCED 0h PeriodCurrentED Used by the host controller to point to the head of one of the periodic lists that will be processed in the current frame. The content of this register is updated by the host controller after a periodic endpoint has been processed. The host controller driver can read the content to determine which endpoint currently is being processed at the time of the reading.
USB host block registers Register bit assignment Bits Access Mnemonic Reset Description D31:04 R/W CHED 0h ControlHeadED The host controller traverses the control list starting with the HcCOntrolHeadED pointer. The content is loaded from the host controller communication area during the host controller initialization. D03:00 N/A Not used 0 Must be written to 0.
USB Controller Module Register bit assignment Bits Access Mnemonic Reset Description D31:04 R/W CCED 0h ControlCurrentED This pointer is advanced to the next endpoint descriptor after serving the present one. The host controller continues processing the list from where it left off in the last frame. When it reaches the end of the control list, the host controller checks the ControlListFilled field (see "HcCommandStatus register," beginning on page 730).
USB host block registers Register bit assignment Bits Access Mnemonic Reset Description D31:04 R/W BHED 0h BulkHeadED The host controller traverses the bulk list starting with the HcBulkHeadED pointer. The content is loaded from the host controller communication area during the host controller initialization. D03:00 N/A Not used 0 Must be written to 0.
USB Controller Module Register bit assignment Bits Access Mnemonic Reset Description D31:04 R/W BCED 0h BulkCurrentED BulkCurrentED is advanced to the next endpoint descriptor after the host controller has served the present endpoint descriptor. The host controller continues processing the list from where it left off in the last frame. When it reaches the end of the bulk list, the host controller checks the ControlListFilled field (see "HcControl register," beginning on page 727).
USB host block registers HcDoneHead register Address: 9010 1030 The HcDoneHead register contains the physical address of the last completed transfer descriptor that was added to the Done queue. In normal operation, the host controller driver should not need to read this register as its content is written periodically to the host controller communication area.
USB Controller Module HcFmInterval register Address: 9010 1034 The HcFmInterval register contains the 14-bit value that indicates the bit time interval in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the full speed maximum packet size that the host controller can transmit or receive without causing a scheduling overrun. The host controller driver can perform minor adjustment on the FrameInterval by writing a new value over the present one at each SOF.
USB host block registers Bits Access Mnemonic Reset Description D13:00 R/W FI 2EDFh FrameInterval Specifies the interval between two consecutive SOFs in bit times. The nominal value is 11,999.
USB Controller Module Register bit assignment Bits Access Mnemonic Reset Description D31 R FRT 0b FrameRemainingToggle Loaded from the FrameIntervalToggle field of the HcFmInterval register (see "HcFmInterval register" on page 747) when FrameRemaining (D13:00 in this register) reaches 0. This bit is used by HCD for synchronization between FrameInterval and FrameRemaining. D30:14 N/A Reserved N/A N/A D13:00 R FR 0h FrameRemaining counter Decremented at each bit time.
USB host block registers Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15:00 R FN 0h FrameNumber Incremented when the HcFmRemaining register (see "HcFmRemaining register" on page 748) is reloaded. The frame number will be rolled over to 0h after ffffh. When entering the USB operational state, FrameNumber is incremented automatically.
USB Controller Module Bits Access Mnemonic Reset Description D13:00 R/W PS 0h PeriodicStart Determines when is the earliest time the host controller should start processing the periodic list. After a hardware reset, the PS field is cleared. The field is then set by the host controller driver during the host controller initialization. The value is calculated as approximately 10% off from the FrameInterval. A typical value is 3E67h.
USB host block registers Register bit assignment Bits Access Mnemonic Reset Description D31:12 N/A Reserved N/A N/A D11:00 R/W LST 0628h LSThreshold Contains a value that is compared to the FrameRemaining field before initiating a low speed (LS) transaction. The transaction is started only if FrameRemaining is greater than or equal to LSThreshold. The value is calculated by the host controller driver, with transmission and setup overhead considerations.
USB Controller Module HcRhDescriptorA register Address: 9010 1048 The HcRhDescriptorA register is the first of two registers describing the characteristics of the root hub. The root hub is the logical hub built into a USB host. Reset values are implementation-specific.
USB host block registers Bits Access Mnemonic Reset Description D11 R/W OCPM IS OverCurrentProtectionMode Describes how the overcurrent status for the root hub ports is reported. At reset, this field should reflect the same mode as PowerSwitchingMode (D08 in this register). The OCPM field is valid only if the NoOverCurrentProtection field (D12 in this register) is cleared. 0 Overcurrent status is reported collectively for all downstream ports. 1 Overcurrent status is reported on a per-port basis.
USB Controller Module HcRhDescriptorB register Address: 9010 104C The HcRhDescriptorB register is the second of two registers describing the characteristics of the root hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementationspecific.
USB host block registers Bits Access Mnemonic Reset Description D15:00 R/W DR IS DeviceRemovable Each bit is dedicated to a root hub port. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0: Reserved Bit 1: Device attached to port #1 Bit 2: Device attached to port #2 ...
USB Controller Module Bits Access Mnemonic Reset Description D17 R/W CCIC 0b OverCurrentIndicatorChange Set by hardware when a change has occurred to the OCI field (bit 01 in this register). The host controller driver clears this bit by writing 1. Writing 0 to this bit has no effect. D16 R/W LPSC 0b LocalPowerStatusChange (LPSC) Not supported; always read as 0.
USB host block registers Bits Access Mnemonic Reset Description D00 R/W LPS 0b LocalPowerStatus (read) Not supported; always read as 0. ClearGlobalPower (write) In global power mode (PowerSwitchingMode=0), this bit is always written to 1 to turn off power to all ports (clear PowerPortStatus). In per-port power mode, this bit clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing 0 to this bit has no effect.
USB Controller Module HcRhPortStatus[1] register Address: 9010 1054 The HcRhPortStatus register controls and reports port events on a per-port basis. The lower word reflects port status; the upper word reflects the status change bits. If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes.
USB host block registers Bits Access Mnemonic Reset Description D18 R/W PSSC 0b PortSuspendStatusChange 0 Resume is not completed 1 Resume completed Set when the full resume sequence has been completed. This sequence includes the 20-s resume pulse, LS EOP, and 3-ms resynchronization delay. The host controller driver writes a 1 to clear this bit. Writing 0 has no effect. This bit also is cleared when ResetStatusChange is set.
USB Controller Module Bits Access Mnemonic Reset Description D09 R/W LSDA Xb LowSpeedDeviceAttached (read) 0 Full speed device attached 1 Low speed device attached Indicates the speed of the device attached to this port. When set, the low speed device is attached to this port. When clear, a full speed device is attached to this port. This field is valid only when CurrentConnectStatus is set.
USB host block registers Bits Access Mnemonic Reset Description D07:05 N/A Not used N/A Always write to 0. D04 R/W PRS 0b PortResetStatus (read) 0 Port reset signal is not active 1 Port reset signal is active When this bit is set by a write to SetPortReset, port reset signalling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared.
USB Controller Module Bits Access Mnemonic Reset Description D02 R/W PSS 0b PortSuspendStatus (read) 0 Port is not suspended 1 Port is suspended Indicates that the port is suspended or in the resume sequence. This bit is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus is cleared.
USB host block registers Bits Access Mnemonic Reset Description D01 R/W PES 0b PortEnableStatus (read) 0 Port is disabled 1 Port is enabled Indicates whether the port is enabled or disabled. The NS9750 can clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error (such as babble) is found. This change also causes PortEnableStatusChange (bit 17 in this register) to be set.
USB Controller Module USB Device Block registers Table 445 provides the addresses of the USB Device Block registers.
USB Device Block registers Endpoint Descriptor #0–#11 registers Address: 9010 2004 / 2008 / 200C / 2010 / 2014 / 2018 / 201C / 2020 / 2024 / 2028 / 202C / 2030 The Endpoint Descriptor registers store the endpoint information. There are 12 registers, one for each endpoint descriptor. Each register contains the same information for the endpoint descriptor.
USB Controller Module Bits Access Mnemonic Reset Description D03:00 R/W EDNBR 4’h0 Endpoint number Table 446: Endpoint Descriptor register (for endpoint descriptors 0–11) USB Device Endpoint FIFO Control and Data registers Table 447 provides the addresses for the endpoint registers found in the application logic that interfaces to the USB device block.
USB Device Endpoint FIFO Control and Data registers Address Register 9010 30A4 FIFO Packet Control #10 9010 30A8 FIFO Packet Control #11 9010 30AC FIFO Packet Control #12 9010 30B0 FIFO Packet Control #13 9010 3100 FIFO Status and Control #1 9010 3108 FIFO Status and Control #2 9010 3110 FIFO Status and Control #3 9010 3118 FIFO Status and Control #4 9010 3120 FIFO Status and Control #5 9010 3128 FIFO Status and Control #6 9010 3130 FIFO Status and Control #7 9010 3138 FIFO Status
USB Controller Module DMA channel FIFO EP number 6 6 4 7 7 5 8 8 6 9 9 7 10 10 8 11 11 9 12 12 10 13 13 11 Table 448: FIFO to DMA channel to endpoint map FIFO Interrupt Status registers The FIFO Interrupt Status registers contain interrupt status information for the device block FIFOs. All status bits are active high (1) and all interrupts are cleared by writing a 1 to the appropriate field.
USB Device Endpoint FIFO Control and Data registers Device endpoint status Table 449 defines the device endpoint status provided for each endpoint FIFO. Firmware uses this information to know which endpoints are active and whether there were any transmission errors. Status Direction Description ACK In Set when an ACK packet is received from the host in response to the previous data packet. For isochronous pipes, the ACK field is asserted automatically for each packet sent to the host.
USB Controller Module FIFO Interrupt Status 0 register Address: 9010 3000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 ACK1 NACK 1 ERROR 1 Reserved 15 14 13 ACK2 NACK 2 ERROR 2 12 11 10 9 8 Reserved Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Not used 0x0000 Always read as 0x0000. D15 RW1TC ACK2 0 Endpoint 0 (CTRL-In) acknowledge status. See Table 449, “USB device endpoint status,” on page 770.
USB Device Endpoint FIFO Control and Data registers 31 30 29 ACK6 NACK 6 ERROR 6 15 14 13 ACK4 NACK 4 ERROR 4 28 27 26 25 24 Reserved 12 11 10 9 8 Reserved 23 22 21 ACK5 NACK 5 ERROR 5 7 6 5 ACK3 NACK 3 ERROR 3 20 19 18 17 16 1 0 Reserved 4 3 2 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31 RW1TC ACK6 0 Endpoint 4 acknowledge status. See Table 449, “USB device endpoint status,” on page 770.
USB Controller Module Bits Access Mnemonic Reset Description D06 RW1TC NACK3 0 Endpoint 1 negative acknowledge status. See Table 449, “USB device endpoint status,” on page 770. D05 RW1TC ERROR3 0 Endpoint 1 error status. See Table 449, “USB device endpoint status,” on page 770. D04:00 N/A Reserved N/A Not valid in DMA mode.
USB Device Endpoint FIFO Control and Data registers Bits Access Mnemonic Reset Description D20:16 N/A Reserved N/A Not valid in DMA mode. D15 RW1TC ACK8 0 Endpoint 6 acknowledge status. See Table 449, “USB device endpoint status,” on page 770. D14 RW1TC NACK8 0 Endpoint 6 negative acknowledge status. See Table 449: "USB device endpoint status" on page 770. D13 RW1TC ERROR8 0 Endpoint 6 error status. See Table 449: "USB device endpoint status" on page 770.
USB Controller Module FIFO Interrupt Status 3 register Address: 9010 3030 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 4 3 2 1 0 Reserved 15 14 13 ACK 12 NACK 12 ERROR 12 12 11 10 9 8 Reserved 7 6 5 ACK 11 NACK 11 ERROR 11 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31:16 N/A Reserved N/A N/A D15 RW1TC ACK12 0 Endpoint 10 acknowledge status. See Table 449: "USB device endpoint status" on page 770.
USB Device Endpoint FIFO Control and Data registers FIFO Interrupt Enable registers The FIFO Interrupt Enable registers contain the interrupt enable information for the device block FIFOs. All interrupts are enabled by writing a 1 and are disabled by writing a 0. The endpoint to register field mapping is identical to the FIFO Interrupt Status registers.
USB Controller Module FIFO Interrupt Enable 1 register Address: 9010 3014 31 30 29 ACK6 NACK 6 ERROR 6 15 14 13 ACK4 NACK 4 ERROR 4 28 27 26 25 24 Reserved 12 11 10 9 8 Reserved 23 22 21 ACK5 NACK 5 ERROR 5 7 6 5 ACK3 NACK 3 ERROR 3 20 19 18 17 16 1 0 Reserved 4 3 2 Reserved Register bit assignment Bits Access Mnemonic Reset Description D31 R/W ACK6 0 Generate an interrupt when ACK6 in FIFO Interrupt Status 1 register is asserted.
USB Device Endpoint FIFO Control and Data registers Bits Access Mnemonic Reset Description D07 R/W ACK3 0 Generate an interrupt when ACK3 in FIFO Interrupt Status 1 register is asserted. D06 R/W NACK3 0 Generate an interrupt when NACK3 in FIFO Interrupt Status 1 register is asserted. D05 R/W ERROR3 0 Generate an interrupts when ERROR3 in FIFO Interrupt Status 1 register is asserted. D04:00 N/A Reserved N/A Not valid in DMA mode.
USB Controller Module Bits Access Mnemonic Reset Description D21 R/W ERROR9 0 Generate an interrupt when ERROR9 in FIFO Interrupt Status 2 register is asserted. D20:16 N/A Reserved N/A Not valid in DMA mode. D15 R/W ACK8 0 Generate an interrupt when ACK8 in FIFO Interrupt Status 2 register is asserted. D14 R/W NACK8 0 Generate an interrupt when NACK8 in FIFO Interrupt Status 2 register is asserted.
USB Device Endpoint FIFO Control and Data registers Register bit assignment Bits Access Mnemonic Reset Description D31:24 N/A Not used 0x00 Always read as 0x00. D23 R/W ACK13 0 Generate an interrupt when ACK13 in FIFO Interrupt Status 3 register is asserted. D22 R/W NACK13 0 Generate an interrupt when NACK13 in FIFO Interrupt Status 3 register is asserted. D21 R/W ERROR13 0 Generate an interrupt when ERROR13 in FIFO Interrupt Status 3 register is asserted.
USB Controller Module 31 30 29 28 27 26 25 Not used 15 24 23 22 21 20 19 13 12 11 10 9 17 16 Not used MAX 14 18 8 7 6 5 4 3 2 1 0 COUNT Register bit assignment Bits Access Mnemonic Reset Description D31:30 N/A Not used 0x0 Always read as 0x0. D29:20 R/W MAX 0x040 Indicates the maximum packet size supported by the associated USB device endpoint.
USB Device Endpoint FIFO Control and Data registers 31 30 29 28 27 26 25 24 23 Reserved 15 14 STATE 13 12 M31 M30 11 22 21 Not used 10 9 8 7 20 TYPE 6 5 4 19 18 CLR DIR 3 2 17 16 FDB 1 0 CIA Register bit assignment Bits Access Mnemonic Reset Description D31:24 N/A Reserved N/A N/A D23:22 R/W Not used 0x0 Always write as 00. D21:20 R/W TYPE 0x0 Type field Defines the endpoint type associated with the FIFO.
USB Controller Module Bits Access Mnemonic Reset Description D15:14 R STATE 0x0 State field Defines the state of the endpoint after the most recent communication with the USB device module. 00 Undefined 01 Data phase transaction 10 Status phase transaction 11 No-data status phase transaction This field is used primarily for diagnostic purposes.
USB Device Endpoint FIFO Control and Data registers 784 NS9750 Hardware Reference
USB Controller Module www.digiembedded.
Timing C H A P T E R 1 7 T his chapter provides the electrical specifications, or timing, integral to the operation of the NS9750. Timing includes information about DC and AC characteristics, output rise and fall timing, and crystal oscillator specifications.
Electrical characteristics Electrical characteristics The NS9750 operates at a 1.5V core, with 3.3V I/O ring voltages. Absolute maximum ratings Permanent device damage can occur if the absolute maximum ratings are exceeded for even an instant. Parameter Symbol† Rating Unit DC supply voltage VDDA -0.3 to +3.9 V DC input voltage VINA -0.3 to VDDA+0.3 V DC output voltage VOUTA -0.3 to VDDA+0.
Timing Maximum power dissipation Table 462 shows the maximum power dissipation, including sleep mode information, for I/O and core. Operation CPU clock Sleep mode with wake up on No PCI No PCI, LCD All ports BBus ports AHB bus ports No wake up ports Total@ 1.7W 200 MHZ Core 1.05 W I/O 0.65 W 1.55 W 1.5 W 350 mW 285 mW 240 mW 180 mW 1W 0.55 W 1W 0.5 W Total @ 1.4 W 162 MHz Core 0.9 W I/O 0.5 W 1.25 W 1.2 W 0.8 W 0.45 W 0.8 W 0.4 W Total @ 1.05 W 125 MHz Core 0.65 W I/O 0.
DC electrical characteristics DC electrical characteristics DC characteristics specify the worst-case DC electrical performance of the I/O buffers that are guaranteed over the specified temperature range. Inputs All electrical inputs are 3.3V interface. Note: VSS = 0V (GND) Sym Parameter VIH High-level input voltage: LVTTL level PCI level Min Low-level input voltage: LVTTL level PCI level Max VIL IIH Condition Value Unit 2.0 0.5VDDA V V 0.8 0.
Timing Symbol Parameter Min VIL Input low level VDI Differential input sensitivity 0.2 VCM Differential common mode range 0.8 Max Units 0.8 V 2.5 Notes V 1 V 2 Table 464: USB DC electrical inputs Notes: 1 |(usb_dp) – (usb_dm)| 2 Includes VDI range. Outputs All electrical outputs are 3.3V interface. Sym Parameter Value Unit VOH High-level output voltage (LVTTL) Min VDDA-0.6 V VOL Low-level output voltage (LVTTL) Max 0.4 V VOH PCI high-level output voltage Min 0.
Reset and edge sensitive input timing requirements Reset and edge sensitive input timing requirements The critical timing requirement is the rise and fall time of the input. If the rise time is too slow for the reset input, the hardware strapping options may be registered incorrectly. If the rise time of a positive-edge-triggered external interrupt is too slow, then an interrupt may be detected on both the rising and falling edge of the input signal.
Timing If an external device driving the reset or edge sensitive input on a Digi processor cannot meet the 500ns maximum rise and fall time requirement, the signal must be buffered with a Schmitt trigger device.
794 NS9750 Hardware Reference Ct 10K DC/DC Regulator 2.4K Sense = 2.93V 3.3V_IN A B 3.3V_IN 3.3V_IN C D C to D Ramp-Down LT1963AEQ-1.5 1.0W Max. 1.5V 3.3V NS9750 CORE I/O Peripherals connected to NS9750 I/O 3.3V_PERPH C to D = 1.5V maintained at 80%, or above, until 3.3V reaches 80% or below. JA = 30 C/W LDO Regulator U2 TPS2022 EN Power Switch 1 Amp U4 3.3V 1.5V D = 3.3V_IN at 2.0V A to B = 1.5V at 80%, or above, preceeds 3.
Timing Memory timing Note: All AC characteristics are measured with 35pF, unless otherwise noted. Memory timing contains parameters and diagrams for both SDRAM and SRAM timing. Table 467 describes the values shown in the SDRAM timing diagrams (Figure 104 through Figure 112). Parm Description Min Max Unit Notes M1 data input setup time to rising 1.6 ns M2 data input hold time to rising 3.3 ns M3 clk_out high to clk_en high 6.1 ns M4 clk_out high to address valid 6.
Memory timing SDRAM burst read (16-bit) pre act read lat d-A d-B clk_out<3:0> M2 M1 data<31:16> M11 M4 addr Note-1 Note-2 M5 data_mask<3:0> M6 dy_cs_n<3:0>* M7 ras_n M8 cas_n M9 we_n Figure 104: SDRAM burst read (16-bit) timing Notes: 796 1 This is the bank and RAS address. 2 This is the CAS address.
Timing SDRAM burst read (16-bit), CAS latency = 3 pre act read lat lat d-A d-B d-C d-D d-E d-F d-G d-H clk_out<3:0> M2 M1 data<31:16> M11 M4 addr Note-1 Note-2 M5 data_mask<3:0> M6 dy_cs_n<3:0>* M7 ras_n M8 cas_n M9 we_n Figure 105: SDRAM burst read (16-bit), CAS latency = 3 timing Notes: 1 This is the bank and RAS address. 2 This is the CAS address. www.digiembedded.
Memory timing SDRAM burst write (16-bit) pre act wr d-A d-B clk_out<3:0> M12 M10 data<31:0> M4 Note-1 addr Note-2 M5 data_mask<3:2> M5 data_mask<1:0>* M6 dy_cs_n<3:0>* M7 ras_n M8 cas_n M9 we_n Figure 106: SDRAM burst write (16-bit) timing Notes: 798 1 This is the bank and RAS address. 2 This is the CAS address.
Timing SDRAM burst read (32-bit) prechg active read cas lat data-A data-B data-C data-D clk_out<3:0> M2 M1 data<31:0> M4 M11 Note-1 addr Note-2 M5 data_mask<3:0>* M6 dy_cs_n<3:0>* M7 ras_n M8 cas_n M9 we_n Figure 107: SDRAM burst read (32-bit) timing Notes: 1 This is the bank and RAS address. 2 This is the CAS address. www.digiembedded.
Memory timing SDRAM burst read (32-bit), CAS latency = 3 pre act read lat lat data-A data-B clk_out<3:0> M2 M1 data<31:0> M4 M11 Note-1 addr Note-2 M5 data_mask<3:0>* M6 dy_cs_n<3:0>* M7 ras_n M8 cas_n M9 we_n Figure 108: SDRAM burst read (32-bit), CAS latency = 3 timing Notes: 800 1 This is the bank and RAS address. 2 This is the CAS address.
Timing SDRAM burst write (32-bit) prechg active wr d-A data-B data-C data-D clk_out M10 M12 data<31:0> M4 Note-1 addr Note-2 M5 data_mask<3:0>* M6 dy_cs_n<3:0> M7 ras_n M8 cas_n M9 we_n Figure 109: SDRAM burst write (32-bit) timing Notes: 1 This is the bank and RAS address. 2 This is the CAS address. www.digiembedded.
Memory timing SDRAM load mode clk_out<3:0> M5 dy_cs_n<3:0>* M7 ras_n M8 cas_n M9 we_n M4 addr<11:0> op code Figure 110: SDRAM load mode timing 802 NS9750 Hardware Reference
Timing SDRAM refresh mode prechg CS0 rf CS1 rf CS2 rf CS3 rf clk_out<3:0> M6 dy_cs0_n M6 dy_cs1_n M6 dy_cs2_n M6 dy_cs3_n M7 ras_n M8 cas_n M9 we_n Figure 111: SDRAM refresh mode timing Clock enable timing clk_out<3:0> M3 M14 clk_en<3:0> M13 SDRAM cycle clk_enable.td Figure 112: Clock enable timing www.digiembedded.
Memory timing Table 468 describes the values shown in the SRAM timing diagrams (Figure 113 through Figure 118).
Timing Static RAM read cycles with 0 wait states CPU clock / 2 M26 M25 data<31:0> M17 M18 addr<27:0> M19 M20 M27 M28 M23 M24 st_cs_n<3:0> oe_n byte_lane<3:0> Figure 113: Static RAM read cycles with 0 wait states timing WTRD = 1 WOEN = 1 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit read cycles. If the PB field is set to 0, the byte_lane signal will always be high. www.digiembedded.
Memory timing Static RAM asynchronous page mode read, WTPG = 1 Note-1 Note-2 Note-2 Note-2 CPU clock / 2 M26 M26 M25 M25 data<31:0> M17 M18 Note-3 addr<27:0> Note-4 M18 Note-5 Note-6 M19 M20 M27 M28 M23 M24 st_cs_n<3:0> oe_n byte_lane<3:0> Note-7 Figure 114: Static RAM asynchronous page mode read, WTPG = 1 timing WTPG = 1 WTRD = 2 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit read cycles.
Timing Static RAM read cycle with configurable wait states CPU clock / 2 M26 M25 data<31:0> M17 M18 addr<27:0> M19 M20 Note-1 st_cs_n<3:0> M27 M28 Note-1 oe_n M23 byte_lane<3:0> M24 Note-1 Figure 115: Static RAM read cycle with configurable wait states WTRD = from 1 to 15 WOEN = from 0 to 15 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit read cycles. If the PB field is set to 0, the byte_lane signal will always be high. www.digiembedded.
Memory timing Static RAM sequential write cycles CPU clock / 2 M15 M16 M17 M18 M19 M20 data<31:0> addr<27:0> st_cs_n<3:0> M21 M22 we_n M23 M24 byte_lane<3:0> M21 byte_lane[3:0] as WE* M22 Note1 Figure 116: Static RAM sequential write cycles WTWR = 0 WWEN = 0 During a 32-bit transfer, all four byte_lane signals will go low. During a 16-bit transfer, two byte_lane signals will go low. During an 8-bit transfer, only one byte_lane signal will go low.
Timing Static RAM write cycle CPU clock / 2 M15 M16 M17 M18 M19 M20 data<31:0> addr<27:0> st_cs_n<3:0> M21 M22 we_n M23 M24 byte_lane<3:0> M21 M22 Note-1 byte_lane[3:0] as WE* Figure 117: Static RAM write cycle WTWR = 0 WWEN = 0 During a 32-bit transfer, all four byte_lane signals will go low. During a 16-bit transfer, two byte_lane signals will go low. During an 8-bit transfer, only one byte_lane signal will go low.
Memory timing Static write cycle with configurable wait states CPU clock / 2 M15 M16 M17 M18 data<31:0> addr<17:0> M19 M20 st_cs_n<3:0> Note-1 M21 we_n M22 Note-2 M23 M24 byte_lane<3:0> Note-3 M21 byte_lane[3:0] as WE* Note-4 M22 Note-5 Figure 118: Static write cycle with configurable wait states WTWR = from 0 to 15 WWEN = from 0 to 15 The WTWR field determines the length on the write cycle. During a 32-bit transfer, all four byte_lane signals will go low.
Timing Slow peripheral acknowledge timing This table describes the values shown in the slow peripheral acknowledge timing diagrams.
Memory timing Slow peripheral acknowledge read 0ns 50ns 100ns 150ns 200ns clk_out<3:0> M32 M26 data<31:0> M17 M18 addr<27:0> M20 M19 M31 st_cs_n<3:0> M27 M28 M23 M24 oe_n byte_lane<3:0> M29 M30 ta_strb Slow peripheral acknowledge write 0ns 50ns 100ns 150ns 200ns clk_out<3:0> M15 M16 M17 M18 data<31:0> addr<27:0> M20 M19 M31 st_cs_n<3:0> M21 M22 we_n M23 M24 byte_lane<3:0> 3 M29 ta_strb 812 NS9750 Hardware Reference M30 6
Timing Ethernet timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. Table 470 describes the values shown in the Ethernet timing diagrams (Figure 119 and Figure 120).
Ethernet timing Ethernet MII timing tx_clk E1 txd[3:0],tx_en,tx_er rx_clk E3 E2 rxd[3:0],rx_en,rx_er E11 cam_req E12 E13 cam_reject E7 mdc E5 E4 mdio (input) E6 mdio (output) Figure 119: Ethernet MII timing 814 NS9750 Hardware Reference
Timing Ethernet RMII timing ref_clk E8 txd[1:0],tx_en E9 E10 rxd[1:0],crs,rx_er E7 mdc E5 E4 mdio (input) E6 mdio (output) Figure 120: Ethernet RMII timing www.digiembedded.
PCI timing PCI timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. Table 471 and Table 472 describe the values shown in the PCI timing diagrams (Figure 121 through Figure 127).
Timing Parameter Description Min Max Units Notes P1 pci_clk_in to signal valid delay 2 10 ns 1 P2 Input setup to pci_clk_in 5 ns 1 P3 Input hold from pci_clk_in 0 ns P4 pci_clk_in to signal active 2 ns 1 P5 pci_clk_in to signal float 28 ns 1 P6 pci_clk_out high time 50%-1 50%+1 ns 2 P7 pci_clk_out low time 50%-1 50%+1 ns 2 P8 pci_clk_in cycle time 30 ns P9 pci_clk_in high time 11 ns P10 pci_clk_in low time 11 ns Table 472: CardBus timing characteristic
PCI timing Internal PCI arbiter timing pci_clk_in Switch Master Switch Master frame_n irdy_n Master 1 Cycle addr ad[31:0] data0 data1 Master 2 Cycle data2 Master 1 Cycle data0 addr addr data0 P3 pci_arb_req_1_n P2 pci_arb_req_2_n P1 pci_arb_gnt_1_n pci_arb_gnt_2_n Figure 121: Internal PCI arbiter timing PCI burst write from NS9750 timing pci_clk_in P1 frame_n P4 P1 P5 addr ad[31:0] data0 data1 data2 data3 data4 data5 data6 data7 P1 cbe_n[3:0] cmd byte enables P1 irdy_n P2 P3
Timing PCI burst read from NS9750 timing pci_clk_in P1 frame_n P4 P1 P5 P2 addr ad[31:0] data0 P3 data1 data2 data3 data4 data5 data6 data7 P1 cbe_n[3:0] cmd byte enables P1 irdy_n P2 P3 trdy_n P2 P3 devsel_n Figure 123: PCI burst read from NS9750 timing The functional timing for trdy_n, devsel_n, and the read data on ad[31:0] shows the fastest possible response from the target.
PCI timing PCI burst read to NS9750 timing pci_clk_in P2 P3 frame_n P2 P4 P1 addr ad[31:0] P5 data0 data1 data2 P2 cbe_n[3:0] data3 data4 data5 data6 data7 P3 cmd byte enables P2 P3 irdy_n P1 trdy_n P1 3x pci_clk_in devsel_n N t Figure 125: PCI burst read to NS9750 timing Note: The functional timing for valid read data on ad[31:0] is just an example. The actual response time will depend on when the PCI bridge gets access to the AHB bus internal to NS9750.
Timing I 2 C timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. Table 473 describes the values shown in the I2C timing diagram (Figure 128). Standard mode Fast mode Min Parm Description Min Max Max Unit C1 iic_sda to iic_scl START hold time 4.0 0.6 μs C2 iic_scl low period 4.7 1.3 μs C3 iic_scl high period 4.7 1.
LCD timing LCD timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. Table 474 describes the values shown in the LCD timing diagrams (Figure 129 through Figure 135).
Timing Parm Description L18 Register Value Units CLCP to data/control (see notes 7 and 8) -1.0 (min) +1.5 (max) ns L19 CLCP high (see notes 8, 9) 50%±0.5ns ns L20 CLCP low (see notes 8, 9) 50%±0.5ns ns L21 TFT VSYNC active to HSYNC active (see note 8) -0.1ns (min) +0.
LCD timing 5 These data widths are supported: — 4-bit mono STN single panel — 8-bit mono STN single panel — 8-bit color STN single panel — 4-bit mono STN dual panel (8 bits to LCD panel) — 8-bit mono STN dual panel (16 bits to LCD panel) — 8-bit color STN dual panel (16 bits to LCD panel) — 24-bit TFT — 18-bit TFT 6 See "LCDTiming0," beginning on page 580, and "LCDTiming1," beginning on page 582, for definitions of the bit fields referred to in this table.
Timing Vertical timing for STN displays L12 L14 L13 CLFP CLLP CLD[7:0] Blank Lines L15 L16 Valid Display Data Blank Lines Valid Display Data Figure 130: Vertical timing parameters for STN displays Horizontal timing for TFT displays L3 L1 L2 L4 CLLP L6 CLCP CLAC L5 CLD[23:0] Blanking Active Display Data Blanking Figure 131: Horizontal timing parameters for TFT displays Vertical timing for TFT displays L8 L7 L9 L10 CLFP L11 CLLP Blanking Active Display Data Blanking CLAC Figure 132: V
LCD timing HSYNC vs VSYNC timing for STN displays L12 L23 L25 CLFP L24 CLLP Figure 133: HSYNC vs VSYNC timing for STN displays HSYNC vs VSYNC timing for TFT displays L22 L21 CLFP CLLP Figure 134: HSYNC vs VSYNC timing for TFT displays LCD output timing L26 L19 CLCP L18 CLD[23:0],CLLP,CLFP,CLLE,CLAC Figure 135: LCD output timing 826 NS9750 Hardware Reference L20
Timing SPI timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. Table 475 describes the values shown in the SPI timing diagrams (Figure 136 through Figure 139).
SPI timing Parm Description Min SP14 SPI enable low setup to first SPI CLK in rising SP15 Max Units Modes Notes 30 ns 0, 3 1 SPI enable low setup to first SPI CLK in falling 30 ns 1, 2 1 SP16 SPI data in setup to SPI CLK in rising 0 ns 0, 3 SP17 SPI data in hold from SPI CLK in rising 60 ns 0, 3 SP18 SPI data in setup to SPI CLK in falling 0 ns 1, 2 SP19 SPI data in hold from SPI CLK in falling 60 ns 1, 2 SP20 SPI CLK in falling to SPI data out valid 20 70 ns 0,
Timing 6 Cload = 10pf for all outputs. 7 SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Channel B/A/C/D Control Register A.
SPI timing SPI slave mode 0 and 1: 2-byte transfer (see note 7) SP14 SP16 SP24 SP25 SP26 S22 SPI CLK In (Mode 0) SP15 SP18 S23 SPI CLK In (Mode 1) SPI Enable SP20 MSB SPI Data Out LSB SP17 SPI Data In SP21 MSB LSB SP19 MSB LSB MSB LSB Figure 138: SPI slave mode 0 and 1 (2-byte transfer) SPI slave mode 2 and 3: 2-byte transfer (see note 7) SP14 SP16 S22 SPI CLK In (Mode 2) SP15 SP18 S23 SPI CLK In (Mode 3) SPI Enable SP20 SPI Data Out MSB SP17 SPI Data In MSB LSB LSB MSB LS
Timing IEEE 1284 timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. Table 476 describes the values shown in the IEEE 1284 timing diagram (Figure 140). Parm Description Min Max Unit Note IE1 Busy-while-Strobe 0 500 ns 1 IE2 Busy high to nAck low 0 IE3 Busy high 1000 ns 2 IE4 nAck low 500 ns 3 IE5 nAck high to Busy low 500 ns 3 ns Table 476: IEEE 1284 timing parameters Notes: 1 The range is 0ns up to one time unit. 2 Two time units.
USB timing USB timing Table 477 and Table 478 describe the values shown in the USB timing diagrams (Figure 141 through Figure 143). Parm Description Min Max Unit Notes U1 Rise time (10% – 90%) 4 20 ns 1 U2 Fall time (10% – 90%) 4 20 ns 1 U3 Differential rise and fall time matching 90 111.
Timing USB differential data timing usb_dp 90% 90% 10% usb_dm 10% U1 U2 Figure 141: USB differential data USB full speed load timing Full Speed Buffer RS Rs - external resistor usb_dp CL = 50pf RS usb_dm CL = 50pf Figure 142: USB full speed load www.digiembedded.
USB timing USB low speed load Low Speed Buffer RS Rs - external resistor usb_dp CL = 200pf to 600pf VDD RS 1.
Timing Reset and hardware strapping timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. Table 479 describes the values shown in the reset and hardware strapping timing diagram (Figure 144).
JTAG timing JTAG timing All AC characteristics are measured with 10pF, unless otherwise noted. Note: Table 480 describes the values shown in the JTAG timing diagram (Figure 145). Parm Description Min Max J1 tms (input) setup to tck rising 5 ns J2 tms (input) hold to tck rising 2 ns J3 tdi (input) setup to tck rising 5 ns J4 tdi (input) hold to tck rising 2 ns J5 tdo (output) to tck falling 2.
Timing Clock timing Note: All AC characteristics are measured with 10pF, unless otherwise noted. The next three timing diagrams pertain to clock timing. USB crystal/external oscillator timing Table 481 describes the values shown in the USB crystal/external oscillator timing diagram (Figure 146). Parm Description Min Max Unit Notes UC1 x1_usb_osc cycle time 20.831 20.835 ns 1 UC2 x1_usb_osc high time (UC1/2) x 0.4 (UC1/2) x 0.6 ns UC3 x1_usb_osc low time (UC1/2) x 0.4 (UC1/2) x 0.
Clock timing LCD input clock timing Table 482 describes the values shown in the LCD input clock timing diagram (Figure 147). Parm Description Min Max LC1 lcdclk cycle time 6.25 LC2 lcdclk high time (LC1/2) x 0.4 (LC1/2) x 0.6 ns LC3 lcdclk low time (LC1/2) x 0.4 (LC1/2) x 0.6 ns Table 482: LCD input clock timing parameters Note: 1 The clock rate supplied on lcdclk is twice the actual LCD clock rate.
Timing System PLL bypass mode timing Table 483 describes the values shown in the system PLL bypass mode timing diagram (Figure 148). Parm Description Min Max Unit Notes SC1 x1_sys_osc cycle time 2.5 5 ns 1 SC2 x1_sys_osc high time (SC1/2) x 0.45 (SC1/2) x 0.55 ns SC3 x1_sys_osc low time (SC1/2) x 0.45 (SC1/2) x 0.55 ns Table 483: System PLL bypass mode timing parameters Note: 1 The system PLL can be bypassed. In this mode, the CPU clock speed is 1/2 of x1_sys_osc.
Packaging C H A P T E R 1 8 T he NS9750 is a complete system-on-chip processor, and includes Ethernet, display support, and a robust peripheral set. NS9750 dimensions and pinout are shown on the following pages.
A Figure 149 displays the top view and dimensions of the NS9750. Figure 150 displays the side and bottom views and dimensions. 0.3 S 35.0 0.3 35.0 X4 0.
Packaging 2.46 MAX A 0.6 + 0.1 0.635 1.27 (1.625) AF AE AD 1.27 AC AB AA Y W V U T B R P N M L 0.635 K 0.35 S J H G F E D C B A 0.20 S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 (1.625) S // 0.75 + 0.15 0.15 M AB Figure 150: NS9750 side and bottom views www.digiembedded.
Figure 151 shows the layout of the NS9750, for use in setting up the board.
Packaging Product specifications These tables provide additional information about the NS9750. ROHS substance PPM level Lead 0 Mercury 0 Cadmium 0 Hexavalent Chromium 0 Polybrominated biphenyls 0 Polybrominated diphenyl ethers 0 Table 484: NS9750 ROHS specifications Component Weight [mg] Material CAS no. Name Weight [mg] Weight [%] Chip 27.037 7440-21-3 Si 27.0370 0.61 Frame 1841.616 223769-10-6 Epoxy resin 865.5600 19.71 7440-50-8 Cu 736.6500 16.77 7440-02-0 Ni 9.
Component Solder ball Total weight Weight [mg] 592.400 Material Weight [%] CAS no. Name 7440-31-5 Sn 571.6700 13.02 7440-22-4 Ag 17.7700 0.40 7440-50-8 Cu 2.9600 0.07 4391.
Index Numerics 10/100 Ethernet MAC 3 1284 parallel peripheral port 5 16-bit byte gap counter 689, 690 16-bit maximum buffer counter 689, 690 16-bit Thumb instruction set 48, 50 32-bit ARM instruction set 48, 50 8-bit Java instruction set 50 A absolute maximum ratings 788 access sequencing and memory width, dynamic memory controller 162 access sequencing and memory width, static memory controller 123 Active Interrupt Level Status register 301 address connectivity 150 address manipulation, ARM926EJ-S 51 addr
about 48 cache format 110 DSP 78 Jazelle (Java) 77 Memory Management Unit. See MMU.
BBus peripheral address map 473 BBus slave and DMA interface module 677-705 CPU mode 677 DMA mode 677 register map 677 BBus subsystem 501 BBus utility 521-542 ARM Wake-up register 541 BBus DMA Interrupt Enable register 537 BBus DMA Interrupt Status register 536 BBus Monitor register 535 Endian Configuration register 539 GPIO Configuration register options 528 GPIO Configuration registers 524-529 GPIO Control registers 529-532 GPIO Status registers 532-535 Master Reset register 523 register addresses 522 USB
Carry Register 2 Mask register 382 Centronics mode. See compatibility mode.
R3, Domain Access Control register 61, 98 R4 register 62 R5, Fault Status registers 62 R6, Fault Address register 64, 97 R7, Cache Operations register 64-68 R8, TLB Operations register 68 R9, Cache Lockdown register 69-73 system control processor registers 51-77 addresses 51 summary 53 terms and abbreviations 52 CPU arbiter, high speed 255 CPU bus arbitration 472 CPU subsystem 255 cross-bridge transaction error handling 407 D data and command FIFOs 675 data structures in LCD panels 570-572 DC electrical ch
DMA read. See also DMA memory-toperipheral transfers. 471 DMA Status and Interrupt Enable register 494 DMA Status/Interrupt Enable register 516 DMA system 5 DMA transfer executing 474 two-channel transfer external-peripheral-initiated 474 processor-initated 474 DMA transfer status 506-508 DMA write. See also DMA peripheral-to- memory transfers.
register 354 Collision Window/Retry register 355 control and status registers 337-396 definition 315 diagram 316 Ethernet front-end (EFE) module. See also Ethernet front-end module.
TX Error Buffer Descriptor Pointer register 390 Ethernet front-end module about 323 Ethernet slave interface 330 features 316 interrupts 331 power down mode 324 receive packet processor 324 resets 332 transferring a frame to system memory 325 transmit packet processor 327 transmitting a frame to the Ethernet MAC 330 Ethernet General Control Register #1 339 Ethernet General Control Register #2 342 Ethernet General Status register 344 Ethernet interface pinout 25 Ethernet Interrupt Enable register 387 Etherne
fly-by mode 502 fly-by peripheral to memory operations 505 Forward Address register 703 Forward Command DMA Control register 689 Forward Command FIFO Read register 686 Forward Data DMA Control register 690 Forward Data FIFO Read register 687 FULL bit 476, 506 FULL bit, Ethernet 326, 328 G gated timer 263 GEN ID register 311 general purpose I/O. See also GPIO.
I I bit, Ethernet 326, 328 I2C bus arbitration 547 command interface 545 Command Transmit Data register 548 Configuration register 552 external addresses 545 locked interrupt driven mode 546 Master Address register 550 master module commands 546 master module flowchart 556 master software driver 555 master/slave interface 543-557 module 544 physical bus 544 register addresses 547 Slave Address register 551 slave module commands 546 slave module flowchart 557 Status Receive Data register 549 timing diagram 8
timing diagram 831 IEEE 1284 General Configuration register 679 IEEE 1284 timing 831 individual interrupts, LCD 566 industry-standard Ethernet interfaces MII 315 RMII 315 initializing PLL parameters 14 initiating a DMA transfer, two channel (AHB) 474 Int Config registers (0-31) 286 register address mapping 286 interrupt aggregation 483 INTERRUPT bit 476 interrupt bit 506 interrupt codes 553 Interrupt Configuration register 267 interrupt controller 267-270 FIQ interrupts 267 interrupt sources 268, 269 IRQ in
color STN panels 562 features 4, 560-564 functional overview 564-567 interrupts 598-599 master bus error interrupt 598 next base update interrupt 599 vertical compare interrupt 598 LCD panel resolution 561 LCD timing diagrams 822-826 LCDControl register 590 LCDInterrupt register 594 LCDINTRENABLE register 589 LCDLPBASE register 587 LCDLPCURR register 594 LCDPalette register 595 LCDStatus register 593 LCDTiming0 register 580 LCDTiming1 register 582 LCDTiming2 register 583 LCDTiming3 register 587 LCDUPBASE re
maximum power dissipation 789 Media Independent Interface. See MII.
Static Memory Turn Round Delay 0-3 registers 239 static memory write control 136-143 Static Memory Write Delay 0-3 registers 238 Static Memory Write Enable Delay 0-3 registers 234 Status register 207 system overview 117 write protection dynamic memory controller 162 static memory controller 122 Memory Management Unit. See MMU.
DMA 5 Ethernet interface pinout 25 external interrupts 7 external peripheral 5 external system bus interface 2 features 2-7 general purpose I/O (GPIO) 6 general purpose timers and counters 6 GPIO MUX 34 I2C pinout 43 I2C port 5 JTAG interface pinout 43 LCD controller 4 LCD module signals 42 operating grades and ambient temperatures 7 PCI CardBus port 3 PCI pinout 28 PCI/CardBus signals 31 peripheral bus 5 pinout 18-46 power ground 46 power management 6 power sequencing 794 processor 2 reserved pins 45 reset
PCI Bridge PCI Error Address register 433 PCI Bridge PCI to AHB Memory Address Translate 0 register 439 PCI Bridge PCI to AHB Memory Address Translate 1 register 440 PCI bus arbiter 407, 418-455 about 418 configuration registers 420-455 functional description 419 register addresses 420 slave interface 420 PCI bus error interrupt 409 PCI Cache Size register 416 PCI CardBus CIS Pointer register 417 PCI central resource functions 458 PCI Class Code register 416 PCI Command register 414 PCI Configuration 0 regi
PCI Arbiter Configuration register 423 PCI Arbiter Interrupt Enable register 425 PCI Arbiter Interrupt Status register 424 PCI Base Address registers 417 PCI BIST register 417 PCI Bridge Address Translation Control register 441 PCI Bridge AHB Error Address register 433 PCI Bridge AHB to PCI Memory Address Translate 0 register 437 PCI Bridge AHB to PCI Memory Address Translate 1 register 438 PCI Bridge AHB-to-PCI IO Address Translate register 439 PCI Bridge Configuration register 432 PCI Bridge Interrupt Ena
Ethernet interface 25 GPIO MUX 34 I2C 43 JTAG interface 43 NS9750 18-46 PCI interface 28 reserved pins 45 system memory interface 18 USB interface 43 pixel serializer 569 PLL configuration 271 PLL Configuration register 299 PLL multiplier values 274 pll_test_n truth/termination table 28 Port Control register 693 Port Status register, host 692 Port Status register, peripheral 694 power down mode, Ethernet 324 power ground 46 power management 6 power sequencing 794 power up/power down sequence, LCD 563 power-
recommended operating conditions 788 Reduced Media Independent Interface. See RMII.
Serial Channel B/A/C/D Control register B 655 Serial Channel B/A/C/D FIFO Data register 665 Serial Channel Status Register A 657 serial port control and status registers 650-666 serial port performance 650 SPI timing diagrams 827-830 structure 644 transmit FIFO interface 647 serial controller, UART 601-639 bit-rate examples 628-629 bit-rate generator 603 features 602 FIFO management 605-608 receive FIFO interface 606 transmit FIFO interface 605 framing structure 604 functions 605 Serial Channel B/A/C/D Bit-
SPI mode 646 individual mode definition 647 individual modes 646 See also serial controller, SPI.
system control module 253-313 Active Interrupt Level Status register 301 AHB Arbiter Gen Configuration register 282 bootstrap initialization 272-276 BRC channel assignment 283 BRC0, BRC1, BRC2, BRC3 registers 283 bus arbiter configuration examples 258 bus interconnection 254 Clock Configuration register 293 definition 253 External Interrupt 0-3 Control register 313 features 254 Gen ID register 311 general purpose timers/counters 263 Int Config registers (0-31) 286 register address mapping 286 interrupt cont
R0, ID code and cache type status registers 55-57 R1, Control register 58-60 R10, TLB Lockdown register 73 R11 register 74 R12 register 74 R13, Process ID register 75-77 R14 register 77 R15, Test and debug register 77 R2, Translation Table Base register 61 R3, Domain Access Control register 61, 98 R4 register 62 R5, Fault Status registers 62 R6, Fault Address register 64, 97 R7, Cache Operations register 64-68 R8, TLB Operations register 68 R9, Cache Lockdown register 69-73 summary 53 System Memory Chip Sel
timing controller, LCD 574 TLB structure 104 transaction ordering, AHB-to-PCI bridge 410 transferring a frame to system memory, Ethernet 325 translation faults 101 Translation Lookaside Buffer (TLB) 78 transmission error handling, USB 714 transmit broadcast packet counter 374 transmit buffer descriptor format Ethernet 327 Transmit Buffer Descriptor Pointer Offset register 394 transmit byte counter 374 transmit deferral packet counter 374 transmit excessive collision packet counter 375 transmit excessive def
780 FIFO Interrupt Status 0 register 771 FIFO Interrupt Status 1 register 771 FIFO Interrupt Status 2 register 773 FIFO Interrupt Status 3 register 775 FIFO Interrupt Status registers 769775 FIFO Packet Control registers 780 FIFO Status and Control registers 781 Global Interrupt Enable register 720 Global Interrupt Status register 721 HcBulkCurrentED register 744 HcBulkHeadED register 743 HcCommandStatus register 730 HcControl register 727 HcControlCurrentED register 742 HcControlHeadED register 741 HcDoneH
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