Manual

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Pullman, WA 99163

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JTAG-SMT2

Programming Module for Xilinx

FPGAs

Revised March 2, 2015

DOC#: 502-251

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 11

Overview

The Joint Test Action Group (JTAG)-SMT2 is a compact, complete and fully self-contained surface-mount

programming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from

all Xilinx Tools, including iMPACT, Chipscope™, and EDK. Users can load the module directly onto a target board

and reflow it like any other component.

The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG

signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up

to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance,

except when actively driven during programming. The SMT2 module is CE certified and fully compliant with EU

RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from

Digilent, Inc.

Users can connect JTAG signals directly to the corresponding FPGA signals, as shown in Fig. 1. For best results,

mount the module adjacent to the edge of the host PCB over a ground plane. Although users may run signal traces

on top of the host PCB beneath the SMT2, Digilent recommends keeping the area immediately beneath the SMT2

clear.

Note: Keep the impedance between the SMT2 and FPGA below 100 Ohms to operate the JTAG at maximum speed.

4 8

GND

TCK

TDI

TMS

GPIO1

GPIO2

GPIO0

TDO

VREF

GND

Vdd (3.3V)

 Small, complete, all-in-one JTAG programming/debugging

solution for Xilinx FPGAs

 Compatible with all Xilinx Tools

 Compatible with IEEE 1149.7-2009 Class T0 – Class T4

(includes 2-Wire JTAG)

 GPIO pin allows debugging software to reset the processor

core of Xilinx’s Zynq® platform

 Single 3.3V supply

 Separate Vref drives JTAG signal voltages; Vref can be any

voltage between 1.8V and 5V.

 High-Speed USB2 port that can drive JTAG/SPI bus at up to

30Mbit/sec (frequency settable by user)

 SPI programming solution (modes 0 and 2 up to 30Mbit/sec,

modes 1 and 3 up to 2Mbit/sec)

 Uses micro-AB USB2 connector

 Small form-factor surface-mount module can be directly

loaded on target boards

 A similar circuit is available as a stand-alone programming

cable; see Digilent’s JTAG-HS2.

Features include:

The JTAG-SMT2

Summary of content (11 pages)

PAGE 1
300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com JTAG-SMT2 Programming Module for Xilinx® FPGAs Revised March 2, 2015 Overview The Joint Test Action Group (JTAG)-SMT2 is a compact, complete and fully self-contained surface-mount programming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from all Xilinx Tools, including iMPACT, Chipscope™, and EDK.
PAGE 2
JTAG-SMT2 Reference Manual 3.3V Vdd 11 VREF USB2 Port 9 TMS 4 TCK 2 TDI 3 TDO GND 3.3V VIO Vdd 11 VIO VREF VIO TMS SS TCK 2 SCK TDI TDI 3 MOSI TDO TDO USB2 Port TCK 1 9 4 TMS 8 VIO GND GND JTAG-SMT2 FPGA 8 MISO 1 GND JTAG-SMT2 FPGA Figure 1. JTAG-SMT2 port connections. Figure SMT2 SPI port –connections. The SMT2 improves upon the SMT1 with the addition of three general purpose IO2.pins (GPIO0 GPIO2) and support for interfacing IEEE 1149.
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JTAG-SMT2 Reference Manual Note: The Xilinx Tools expect GPIO2/CS3 to be connected to the SRST_B pin on a Zynq chip. As a result, SPI ports 6 and 7 may not be used for SPI communication if the Xilinx Tools are going to be used to communicate with the SMT2. Software Support In addition to working seamlessly with all Xilinx Tools, Digilent’s Adept software and the Adept software development kit (SDK) support the SMT2 module.
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JTAG-SMT2 Reference Manual 2-Wire Star Topology 4-Wire Star Topology Host + JTAG-SMT2 (DTS) TMS TMSC TDI TCK TDIC Target TCKC System 0 TDO TDOC Host + JTAG-SMT2 (DTS) TMS TDI TCK TDO TMSC TDIC Target TCKC System 0 TDOC TMSC TDIC Target TCKC System 1 TDOC TMSC TDIC Target TCKC System 1 TDOC TMSC TDIC Target TCKC System N TDOC TMSC TDIC Target TCKC System N TDOC Figure 4. 4-Wire and 2-Wire star topology. The IEEE 1149.
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JTAG-SMT2 Reference Manual VIO 3.3V VIO VIO 200 VDD VREF TMS TMSC JTAGSMT2 TDI TDIC TDO TDOC GND TCK TCKC 1149.7 Target System GND Figure 6. Adding a current limiting resistor. VIO 3.3V VIO 200 VDD VREF VIO TMS TMSC JTAGSMT2 TDI TDIC TDO TDOC GND TCK TCKC 1149.7 Target System GND Figure 7. 200 Ohm resistor limiting current flow.
PAGE 6
JTAG-SMT2 Reference Manual When customers use the JTAG-SMT2 to interface the scan chain of Xilinx’s Zynq platform, they should connect the GPIO2 pin of the SMT2 to the Zynq’s PS_SRST_B pin. This connection allows the Xilinx Tools to reset the Zynq’s processor core at various times during debugging operations. Please see the following “Application Examples” section for more information. Note: The Xilinx tools expect GPIO2 to be connected to the SRST_B pin on a Zynq chip.
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JTAG-SMT2 Reference Manual Example 2: Interfacing a Zynq-7000 that uses different voltages for VCCO_0 and VCCO_MIO1 Figure 10 demonstrates how to connect the JTAG-SMT2 to Xilinx’s Zynq-7000 silicon when different voltages supply the VCCO_0 (Programmable Logic Bank 0 Power Supply) and VCCO_MIO1 (Processor MIO Bank 1 Power Supply). If the Zynq’s JTAG pins are operating at a different voltage than the PS_SRST_B, it requires an external buffer to adjust the level of the GPIO2 signal. The example in Fig.
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JTAG-SMT2 Reference Manual Example 3: Interfacing a Zynq-7000 while retaining the Xilinx JTAG Header Figure 11 below demonstrates how to connect the JTAG-SMT2 to Xilinx’s Zynq-7000 silicon alongside Xilinx’s 14-pin JTAG header. In this example the open drain buffers allow both the SMT2 and Xilinx JTAG Header to drive the PS_SRST_B pin, which may operate a different voltage than the Zynq’s JTAG pins. Xilinx JTAG Header VCCO_0 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 100 50 100 VCCO_MIO1 3.
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JTAG-SMT2 Reference Manual Mechanical Information 5mm 11 8 5mm 3.5mm 19.5mm 5mm 2.2mm Electrical Keepout 6.2mm 4mm 3 4 3.0mm 2 3.5mm 5mm 1 2 3mm 3 4 5 4mm Pads on bottom PCB surface 5 2.6mm 1 6 2.45 mm 21.75mm 6 PCB Edge Electrical Keepout 8 7 2.2mm 2.6mm 9 7 6.2mm 3.0mm 10 2mm 2mm 15mm Recommended PCB Land Pattern SMT2 Top View Absolute Maximum Ratings Symbol Parameter Condition Min Max Unit Vdd Operating supply voltage -0.3 4.
PAGE 10
JTAG-SMT2 Reference Manual DC Operating Characteristics Symbol Parameter Min Typ Max Unit Vdd Operating supply voltage 2.97 3.3 3.63 Volts Vref I/O reference/supply voltage 1.65 2.5/3.3 5.5 Volts TDO, GPIO0, GPIO1, GPIO2 Input High Voltage (VIH) 1.62 5.5 Volts Input Low Voltage (VIL) 0 0.65 Volts TMS, TCK, TDI, GPIO0, GPIO1, GPIO2 Output High (VOH) 0.85 x Vref 0.95 x Vref Vref Volts Output Low (VOL) 0 0.05 x Vref 0.
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JTAG-SMT2 Reference Manual Limit time above 205°C to less than 110s Figure 13.JTAG-SMT2 reflow temperature over time. Packaging Digilent ships small quantities of less than 20 per order individually packaged in antistatic bags. Digilent will pack and ship larger quantities in groups of 80 positioned in an antistatic bubble tray (see Fig. 14). 35cm 28cm Figure 14. JTAG-SMT2 shipping arrangement. Copyright Digilent, Inc. All rights reserved.