User Manual

With VVSET_VCCIO ϵ (0…3V), VCCIO_PROG could be theoretically set in the range: VCCIO_PROG ϵ (1.02V…3.42V). IC15 is a
current shunt amplifier, with a gain of 100. With Vref = 0.75V and R115 = 50mΩ, the output voltage is:
IC14 is a window comparator: FAULT_USR is logical LOW, when VISNS_USR is either more than 1.5V (IVCCIO_USR>150mA) or
less than 0.66V (IVCCIO_USR←18mA). If this happens, the FPGA turns EN_PWR_USR to LOW, which turns both Q1A and Q1B
OFF, to protect VCCIO_USR against overcurrent and reverse current respectively. VCCIO_USR is halved to VSNS_USR, for being
monitored.
Figure 13. VCCIO_PROG supply. []
Figure 12. Internal voltage supplies. []
4.2 Programmable power supply
IC13 in Figure 13 generates the VCCIO_PROG, the variable voltage to supply the input and IO banks of the FPGA:
V
V CCIO _ PROG
= V
FB
∙ (1 + + ) − V
V SET _ V CCIO
∙ = 3.42 V − V
V SET _ V CCIO
∙ 0.82 (3)
R
144
R
146
R
144
R
149
R
144
R
146
V
ISNS _ USR
= 100 ∙ ( V
IN +
− V
IN −
) + 0.75 V = 5 ∙ I
V CCIO _ USR
+ 0.75 V (4)