User Manual

Figure 19. DDR3 memory. []
The USB interface performs two tasks:
Programming the FPGA: There is no non-volatile FPGA configuration memory on the Digital Discovery. The WaveForms
software identifies the connected device and downloads an appropriate .bit file at power-up, via a Digilent USB-JTAG interface.
Adept run-time is used for low level protocols.
Data exchange: All instrument configuration data, acquired data and status information is handled via a Digilent synchronous
parallel bus and USB interface. Speed up to 20MB/sec. is reached, depending on USB port type and load as well as PC
performance.
The core of the Digital Discovery is the Xilinx Spartan6 FPGA circuit XC6SLX25. The configured logic performs:
Clock management (12MHz and 60 MHz () for USB communication, 100MHz and 800MHz for data sampling)
Acquisition control and Data Storage (Logic Analyzer)
Digital signal synthesis (for pattern generator and bus protocol controllers)
Trigger system (trigger detection and distribution for all instruments)
Power supplies control and instruments enabling
Power and temperature monitoring
Calibration memory control
Communication with the PC (settings, status data)
Block
RAM () of the FPGA is used for signal synthesis. External DDR3 memory is used for data acquisition.
6. USB Controller
7. FPGA