User Manual

Detail of the trigger system is shown in Figure 20. Each instrument generates a trigger signal when a trigger condition is met. Each
trigger signal (including external triggers) can trigger any instrument and drive the external trigger outputs. This way, all the instruments
can synchronize to each other.
Figure 20. FPGA configuration trigger block diagram. []
Figure 21 shows the connections to the FPGA banks 0, 1 and 3.
Bank 0 is used for IOs. DIO_FPGA pins are the actual input/output pins to be used with the Pattern Generator, Static IO and Logic
Analyzer. A DIO_PULL pin can add Pull-Up or Pull-Down resistors to the associated DIO_FPGA pin (see Figure 4).
Bank 1 is used for high speed Logic Analyzer inputs. DIN_FPGA are the actual input pins, while DIN_VREF_H and DIN_VREF_L set
the reference voltage for the input dividers (see Figure 9).
Bank 3 is used as port for the DDR3 memory.