User Manual

signal is read at the FPGA pin and does not propagate through the external DIO circuitry. Consequently, when combining DIN and
DIO pins in the Logic Analyzer, misalignments can be observed, at high acquisition rate.
Available combinations in WaveForms: - 200MHz, DIN0…23, DIO24…31 - 200MHz, DIO24…39, DIN0…15 - 400MHz, DIN0…
15 - 400MHz, DIO24…39 - 800MHz, DIN0…7 - 800MHz, DIO24…31
The FPGA DIN and DIO pins are set to LVCMOS18_JEDEC IOSTANDARD. The supply voltage of the associated FPGA banks is
set (by user) to any value from 1.2V to 3.3V. The threshold level (at the FPGA pins) is about 45% of the bank supply voltage. For
standard voltages of: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, the threshold levels (at the FPGA pins) are: 0.58V, 0.7V, 0.82V, 1.1V and 1.42V
respectively.
Setting the voltage to 3.3V, 5V logic inputs are tolerated but the input threshold is 1.42V. LVCMOS 3.3V output signals are compatible
to most external logical circuits supplied with 5V.
Trigger Detectors and Trigger Distribution Networks are implemented in the FPGA. This allows real time triggering and cross-
triggering of different instruments within the Digital Discovery device. Using external Trigger inputs/outputs, cross-triggering between
multiple Digital Discovery devices is possible.
The 16 DIO lines are primarily intended for the Pattern Generator, protocol controllers and Static IO instruments. For user
convenience, some or all of them can be used by the Logic Analyzer also (see footnote 2). However, DIO input circuitry is different
compared to DIN. Even more, when driving a DIO pin with the Pattern Generator and reading it back with the Logic Analyzer, the
signal is read at the FPGA pin and does not propagate through the external DIO circuitry. Consequently, when combining DIN and
DIO pins in the Logic Analyzer, misalignments can be observed, at high acquisition rate.
Real time implemented in the FPGA configuration.
The FPGA DIN and DIO pins are set to LVCMOS18_JEDEC IOSTANDARD. The supply voltage of the associated FPGA banks is
set (by user) to any value from 1.2V to 3.3V. The threshold level (at the FPGA pins) is about 45% of the bank supply voltage. For
standard voltages of: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, the threshold levels (at the FPGA pins) are: 0.58V, 0.7V, 0.82V, 1.1V and 1.42V
respectively.
The FPGA DIN and DIO pins are set to LVCMOS18_JEDEC IOSTANDARD. The supply voltage of the associated FPGA banks is
set (by user) to any value from 1.2V to 3.3V. The threshold level (at the FPGA pins) is about 45% of the bank supply voltage. For
standard voltages of: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, the threshold levels (at the FPGA pins) are: 0.58V, 0.7V, 0.82V, 1.1V and 1.42V
respectively.
Setting the voltage to 3.3V, 5V logic inputs are tolerated but the input threshold is 1.42V. LVCMOS 3.3V output signals are compatible
to most external logical circuits supplied with 5V.
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