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1300 Henley Court

Pullman, WA 99163

509.334.6306

www.digilentinc.com

Basys 3™ FPGA Board Reference Manual

Revised August 12, 2014

This manual applies to the Basys 3 rev. C

DOC#: 502-183

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 19

Overview

The Basys 3 board is a complete, ready-to-use digital circuit development platform based on the latest Artix®-7

Field Programmable Gate Array (FPGA) from Xilinx®. With its high-capacity FPGA (Xilinx part number XC7A35T-

1CPG236C), low overall cost, and collection of USB, VGA, and other ports, the Basys 3 can host designs ranging

from introductory combinational circuits to complex sequential circuits like embedded processors and controllers.

It includes enough switches, LEDs, and other I/O devices to allow a large number of designs to be completed

without the need for any additional hardware, and enough uncommitted FPGA I/O pins to allow designs to be

expanded using Digilent Pmods or other custom boards and circuits.

The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and more

resources than earlier designs. Artix-7 35T features include:

The Basys 3 also offers an improved collection of ports and peripherals, including:

 16 user switches

 16 user LEDs

 5 user pushbuttons

 4-digit 7-segment display

 Three Pmod connectors

 Pmod for XADC signals

 12-bit VGA output

 USB-UART Bridge

 Serial Flash

 Digilent USB-JTAG port for

FPGA programming and

communication

 USB HID Host for mice, keyboards

and memory sticks

The Basys 3 works with Xilinx's new high-performance Vivado™

Design Suite. Vivado includes many new tools and

design flows that facilitate and enhance the latest design methods. It runs faster, allows better use of FPGA

resources, and allows designers to focus their time evaluating design alternatives. The System Edition includes an

on-chip logic analyzer, high-level synthesis tool, other cutting-edge tools, and the free WebPACK™ version allows

Basys 3 designs to be created at no additional cost.

The Basys 3.

 33,280 logic cells in 5200 slices (each slice contains four

6-input LUTs and 8 flip-flops)

 1,800 Kbits of fast block RAM

 Five clock management tiles, each with a phase-locked

loop (PLL)

 90 DSP slices

 Internal clock speeds exceeding 450MHz

 On-chip analog-to-digital converter (XADC)

Summary of content (19 pages)

PAGE 1
300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com Basys 3™ FPGA Board Reference Manual Revised August 12, 2014 This manual applies to the Basys 3 rev. C Overview The Basys 3 board is a complete, ready-to-use digital circuit development platform based on the latest Artix®-7 Field Programmable Gate Array (FPGA) from Xilinx®.
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Basys 3™ FPGA Board Reference Manual 16 15 13 14 11 12 10 9 1 8 2 2 7 3 2 6 4 5 Figure 1. Basys 3 FPGA board with callouts.
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Basys 3™ FPGA Board Reference Manual Power Switch (SW16) 5V External Supply - + JP2 ON/OFF Type A USB Host Connector (J2) J6 Micro-USB Port (J4) Power Source Select VIN2 EN2 2A PGOOD2 3.3V VIN1 EN1 1A PGOOD1 1.0V IC10: LTC3633 JP2 USB VU5V0 Power On LED (LD20) EXTERNAL VIN PGOOD EN 300 mA 1.8V IC11: LTC3621 Figure 2. Basys 3 power circuit. The USB port can deliver enough power for the vast majority of designs.
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Basys 3™ FPGA Board Reference Manual 2 FPGA Configuration After power-on, the Artix-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of three ways: 1. 2. 3. A PC can use the Digilent USB-JTAG circuitry (portJ4, labeled "PROG") to program the FPGA any time the power is on. A file stored in the nonvolatile serial (SPI) flash device can be transferred to the FPGA using the SPI port.
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Basys 3™ FPGA Board Reference Manual 2.1 JTAG Programming The Xilinx Tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J4) or an external JTAG programmer, such as the Digilent JTAG-HS2 attached to port J5 (located below port JA).
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Basys 3™ FPGA Board Reference Manual When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if a USB keyboard is plugged in, a rapid blink will signal the receipt of an HID input report from the keyboard. 3 Memory The Basys 3 board contains a 32Mbit non-volatile serial Flash device, which is attached to the Artix-7 FPGA using a dedicated quad-mode (x4) SPI bus.
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Basys 3™ FPGA Board Reference Manual 5 USB-UART Bridge (Serial Port) The Basys 3 includes an FTDI FT2232HQ USB-UART bridge (attached to connector J4) that allows you to use PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD).
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Basys 3™ FPGA Board Reference Manual 6.1 HID Controller The Auxiliary Function microcontroller hides the USB HID protocol from the FPGA and emulates an old-style PS/2 bus. The microcontroller behaves just like a PS/2 keyboard or mouse would. This means new designs can re-use existing PS/2 IP cores. Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host.
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Basys 3™ FPGA Board Reference Manual ESC 76 `~ 0E 1! 16 TAB 0D F1 05 F2 06 F3 04 F4 0C 2@ 1E 3# 26 4$ 25 5% 2E Q 15 Caps Lock 58 Shift 12 W 1D A 1C S 1B Z 1Z Ctrl 14 E 24 R 2D D 23 X 22 F5 03 6^ 36 T 2C F 2B C 21 Alt 11 F7 83 7& 3D Y 35 G 34 V 2A F6 0B 8* 3E U 3C H 33 B 32 F8 0A 9( 46 I 43 J 3B N 31 F9 01 0) 45 O 44 K 42 M 3A F10 09 -_ 4E P 4D L 4B ,< 41 Space 29 =+ 55 [{ 54 ;: 4C >. 49 /? 4A Alt E0 11 F11 78 F12 07 BackSpace 66 ]} 5B '" 52 \| 5D Enter 5A Shift
PAGE 10
Basys 3™ FPGA Board Reference Manual The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a '1' indicates a negative number).
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Basys 3™ FPGA Board Reference Manual 5 1 10 6 15 11 G19 H19 J19 N19 J17 H17 G17 D17 N18 L18 K18 J18 P19 R19 Pin 1: Red Pin 2: Grn Pin 3: Blue Pin 13: HS Pin 14: VS RED0 4KW RED1 2KW Pin 5: GND Pin 6: Red GND Pin 7: Grn GND Pin 8: Blu GND Pin 10: Sync GND RED2 1KW RED3 510W GRN0 4KW GRN1 2KW RED GRN2 1KW GRN GRN3 510W BLU BLU0 4KW BLU1 2KW BLU2 1KW BLU3 510W HS VS HD-DB15 HSYNC 100W VSYNC 100W Artix-7 7.
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Basys 3™ FPGA Board Reference Manual Anode (entire screen) Cathode ray tube Deflection coils Grid Electron guns (Red, Blue, Green) Cathode ray R,G,B signals (to guns) VGA cable High voltage deflection grid supply (>20kV) control control gun control Figure 12. Color CRT display. Electron beams emanate from "electron guns" which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a "grid.
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Basys 3™ FPGA Board Reference Manual pixel 0,0 pixel 0,639 640 pixels per row are displayed during forward beam trace Display Surface pixel 479,0 Retrace - no information displayed during this time pixel 479,639 Stable current ramp - information is displayed during this time Current waveform through horizontal defletion coil Total horizontal time Horizontal display time retrace time time HS "front porch" Horizontal sync signal sets retrace frequency "back porch" Figure 13.
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Basys 3™ FPGA Board Reference Manual TS Tfp Tdisp T pw Tbp Horiz. Sync Vertical Sync Time Clocks Lines Time Clks Symbol Parameter TS Sync pulse T disp Display time 16.7ms 416,800 521 32 us 800 15.36ms 384,000 480 25.6 us 640 T pw Pulse width 64 us 1,600 2 3.84 us 96 T fp Front porch 320 us 8,000 10 640 ns 16 T bp Back porch 928 us 23,200 29 1.92 us 48 Figure 14. Signal timings for a 640-pixel by 480 row display using a 25 MHz pixel clock and 60 Hz vertical refresh.
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Basys 3™ FPGA Board Reference Manual 3.3V U16 E19 U19 T17 V19 T18 W18 U15 U17 U14 V14 U18 V13 V3 W3 Artix-7 U3 P3 N3 V17 P1 L1 W19 BTNL BTNR Buttons BTNU BTND BTNC 3.3V SW0 SW1 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LEDs V16 3.
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Basys 3™ FPGA Board Reference Manual Figure 17. An un-illuminated seven-segment display and nine illumination patterns corresponding to decimal digits. The anodes of the seven LEDs forming each digit are tied together into one "common anode" circuit node, but the LED cathodes remain separate, as shown in Fig. 18. The common anode signals are available as four "digit enable" input signals to the 4-digit display.
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Basys 3™ FPGA Board Reference Manual in digit position 1. Then, if AN1 is asserted while CA, CB, and CC are asserted, a "7" will be displayed in digit position 2. If AN0, CB, and CC are driven for 4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless succession, the display will show "71" in the first two digits. An example timing diagram for a four-digit controller is shown in Fig. 19.
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Basys 3™ FPGA Board Reference Manual Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/Ds, D/As, motor drivers, sensors, and other functions. See www.digilentinc.com for more information. 9.1 Dual Analog/Digital Pmod The on-board Pmod expansion connector, labeled "JXADC", is wired to the auxiliary analog input pins of the FPGA.
PAGE 19
Basys 3™ FPGA Board Reference Manual 10 Built-In Self-Test A demonstration configuration is loaded into the SPI Flash device on the Basys 3 board during manufacturing. The source code and prebuilt bitstream for this design are available for download from the Digilent website. If the demo configuration is present in the SPI Flash device and the Basys 3 board is powered on in SPI mode, the demo project will allow basic hardware verification.