Datasheet

 2010 Microchip Technology Inc. DS39935C-page 107
ENC424J600/624J600
REGISTER 11-1: MACON1: MAC CONTROL REGISTER 1
R/W-x R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
r r — — r r r r
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1
— — — LOOPBK r RXPAUS PASSALL r
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
Reserved: Write as ‘0’
bit 13-12
Unimplemented: Read as ‘0’
bit 11-8
Reserved: Write as ‘0’
bit 7-5
Unimplemented: Read as ‘0’
bit 4
LOOPBK: MAC Loopback Enable bit
1 = Transmitted packets are looped back inside the MAC before reaching the PHY
0 = Normal operation
bit 3
Reserved: Write as ‘1’
bit 2
RXPAUS: Pause Control Frame Reception Enable bit
1 = Inhibit transmissions when pause control frames are received (normal operation)
0 = Ignore pause control frames which are received
bit 1
PASSALL: Pass All Received Frames Enable bit
1 = Control frames received by the MAC are written into the receive buffer if not filtered out
0 = Control frames are discarded after being processed by the MAC (normal operation)
bit 0
Reserved: Write as ‘1’