Datasheet

 2010 Microchip Technology Inc. DS39935C-page 111
ENC424J600/624J600
REGISTER 12-2: PHSTAT1: PHY STATUS REGISTER 1
R-0 R-1
(1)
R-1
(1)
R-1
(1)
R-1
(1)
R-0 R-0 R-0
r FULL100 HALF100 FULL10 HALF10 r r r
bit 15 bit 8
R-0 R-0 R-0 R/LH-0 R-1
(1)
R/LL-0 R-0 R-1
(1)
r r ANDONE LRFAULT ANABLE LLSTAT r EXTREGS
bit 7 bit 0
Legend: LL = Latch Low bit U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit LH = Latch High bit LL = Latch-Low bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15
Reserved: Read as ‘0’
bit 14
FULL100: 100Base-TX Full-Duplex Ability Status bit
1 = PHY is capable of 100Base-TX full-duplex operation
(1)
bit 13 HALF100: 100Base-TX Half-Duplex Ability Status bit
1 = PHY is capable of 100Base-TX half-duplex operation
(1)
bit 12 FULL10: 10Base-T Full-Duplex Ability Status bit
1 = PHY is capable of 10Base-T full-duplex operation
(1)
bit 11 HALF10: 10Base-T Half-Duplex Ability Status bit
1 = PHY is capable of 10Base-T half-duplex operation
(1)
bit 10-6 Reserved: Ignore on read
bit 5
ANDONE: Auto-Negotiation Done Status bit
1 = Auto-negotiation is complete
0 = Auto-negotiation is disabled or still in progress
bit 4
LRFAULT: Latching Remote Fault Condition Status bit
1 = Remote Fault condition has been detected. This bit latches high and automatically returns to ‘0’
after PHSTAT1 is read.
0 = No remote Fault has been detected since the last read of PHSTAT1
bit 3
ANABLE: Auto-Negotiation Ability Status bit
1 = PHY is capable of auto-negotiation
(1)
bit 2 LLSTAT: Latching Link Status bit
1 = Ethernet link is established and has stayed continuously established since the last read of
PHSTAT1
0 = Ethernet link is not established or was not established for a period since the last read of PHSTAT1
bit 1
Reserved: Ignore on read
bit 0
EXTREGS: Extended Capabilities Registers Present Status bit
1 = PHY has extended capability registers at addresses, 16 thru 31
(1)
Note 1: This is the only valid state for this bit; a ‘0’ represents an invalid condition.