Datasheet

 2010 Microchip Technology Inc. DS39935C-page 115

ENC424J600/624J600

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

r r r r r r r r

bit 15 bit 8

R-0 R-0 R-0 R/LH-0 R-0 R-0 R/LH-0 R-0

r r rPDFLTr r LPARCD LPANABL

bit 7 bit 0

Legend: LH = Latch High bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

Reserved: Ignore on read

bit 4

PDFLT: Parallel Detection Fault Status bit

1 = Parallel detection did not detect a valid link partner; automatically cleared when register is read

0 = Parallel detection is still in progress or a valid link partner is connected

bit 3-2

Reserved: Ignore on read

bit 1

LPARCD: Link Partner Abilities Received Status bit

1 = PHANLPA register has been written with a new value from the link partner; automatically cleared

when register is read

0 = PHANLPA contents have not changed since the last read of PHANE

bit 0

LPANABL: Link Partner Auto-Negotiation Able Status bit

1 = Link partner implements auto-negotiation

0 = Link partner does not implement auto-negotiation