Datasheet

 2010 Microchip Technology Inc. DS39935C-page 117
ENC424J600/624J600
13.0 INTERRUPTS
ENC424J600/624J600 devices have multiple interrupt
sources tied to a single output pin, allowing the device
to signal the occurrence of events to the host controller.
The interrupt pin is active-low and is designed for use
by host controllers that can detect falling edges.
Interrupts can also be used on a polling basis without
connecting the interrupt pin. To use interrupts in this
manner, monitor the INT bit (ESTAT<15>) on a periodic
basis.
Interrupts are managed by two registers. The EIE reg-
ister contains the individual interrupt enable bits for
each interrupt driven by the MAC and cryptographic
components. The EIR register holds the individual
interrupt flags. When an interrupt occurs, the
corresponding interrupt flag is set. If the interrupt is
enabled and the INTIE (EIE<15>) global interrupt
enable bit is set, the INT
pin is driven low and the INT
flag (ESTAT<15>) becomes set. This logic is shown in
Figure 13-1.
Even when an interrupt is not enabled, its corresponding
interrupt flags are still set when the interrupt condition
occurs. This allows the host controller to poll for certain
lower priority events while using the interrupt pin for
more important tasks.
When an enabled interrupt occurs, the INT
pin remains
low until all flags causing interrupts are cleared or
masked off (the enable bit is cleared). If more than one
interrupt source is enabled, the host controller must poll
each flag to determine the source(s) of the interrupt. A
good practice is for the host controller to clear the
Global Interrupt Enable bit, INTIE (EIE<15>), immedi-
ately after an interrupt event. This causes the interrupt
pin to return to the non-asserted (high) state. Once the
interrupt has been serviced, the INTIE bit is set again
to re-enable interrupts. If a new interrupt occurs while
servicing another, the act of resetting the global enable
bit will cause a new falling edge to occur on the
interrupt pin and ensure that the host does not miss any
events.
When clearing EIR interrupt flags, it is required that bit-
oriented operations be used. These include Bit Field
Set and Bit Field Clear opcodes for the SPI interface,
and using the Bit Set and Bit Clear registers for the PSP
interfaces. This procedure ensures that interrupts
occurring during the write procedure are not
inadvertently missed.
FIGURE 13-1: ENC424J600/624J600 INTERRUPT LOGIC
INT
INTIE
LINKIE
LINKIF
AESIE
AESIF
HASHIE
HASHIF
MODEXIE
MODEXIF
EIR/EIE
RXABTIE
RXABTIF
TXABTIE
TXABTIF
TXIE
TXIF
DMAIE
DMAIF
PKTIE
PKTIF
PCFULIE
PCFULIF