Datasheet

 2010 Microchip Technology Inc. DS39935C-page 121
ENC424J600/624J600
13.1 Interrupt Sources
ENC424J600/624J600 devices have multiple interrupt
sources, each individually selectable. The various
interrupt sources are described in the following sections.
For any of the following interrupts to propagate out of
the device, the INTIE (EIE<15>) global interrupt enable
must be set.
13.1.1 MODULAR EXPONENTIATION
COMPLETE
The modular exponentiation complete interrupt occurs
when a modular exponentiation operation is com-
pleted. This flag is set when MODEXST (ECON1<15>)
is cleared. The interrupt should be cleared by software
once it has been serviced.
To enable the modular exponentiation complete
interrupt, set MODEXIE (EIE<14>).
For more information on the modular exponentiation
feature, refer to
Section 15.1 “Modular Exponentiation”.
13.1.2 MD5/SHA-1 HASH COMPLETE
The MD5/SHA-1 hash complete interrupt occurs when
the hashing module completes a block or calculation.
The interrupt flag is required when using the hashing
engine; therefore, the flag must be cleared by software
after the interrupt has been serviced.
To enable the MD5/SHA-1 complete interrupt, set
HASHIE (EIE<13>).
For more information on the MD5/SHA-1 hashing feature,
refer to
Section 15.2 “MD5 and SHA-1 Hashing”.
13.1.3 AES COMPLETE
The Advanced Encryption Standard (AES) complete
interrupt occurs when a block has been encrypted or
decrypted using the AES engine. This flag is set when
AESST (ECON1<11>) is cleared. The interrupt should
be cleared by software once it has been serviced.
To enable the AES complete interrupt, set AESIE
(EIE<12>).
For more information on the Advanced Encryption
Standard engine, refer to
Section 15.3 “Advanced
Encryption Standard (AES)”
.
13.1.4 LINK CHANGE
The link change interrupt occurs when the PHY link
status changes. This flag is set by hardware when a link
has either been established or broken between the
device and a remote Ethernet partner. The current link
status can be read from PHYLNK (ESTAT<8>). The
interrupt should be cleared by software once it has
been serviced.
To enable the link change interrupt, set LINKIE
(EIE<11>).
13.1.5 RECEIVED PACKET PENDING
The received packet pending interrupt occurs when
one or more frames have been received and are ready
for software processing. This flag is set when the
PKTCNT<7:0> (ESTAT<7:0>) bits are non-zero. This
interrupt flag is read-only and will automatically clear
when the PKTCNT bits are decremented to zero. For
more details about receiving and processing incoming
frames, refer to
Section 9.0 “Transmitting and
Receiving Packets”
.
To enable the received packet pending interrupt, set
PKTIE (EIE<6>). The corresponding interrupt flag is
PKTIF (EIR<6>).
13.1.6 DMA COMPLETE
The DMA complete interrupt occurs when a DMA oper-
ation (either copy or checksum calculation) completes.
This flag is set when DMAST (ECON1<5>) is cleared.
The interrupt should be cleared by software once it has
been serviced.
To enable the DMA complete interrupt, set DMAIE
(EIE<5>).
13.1.7 TRANSMIT COMPLETE
The transmit complete interrupt occurs when the trans-
mission of a frame has ended (whether or not it was
successful). This flag is set when TXRTS (ECON1<1>)
is cleared. The interrupt should be cleared by software
once it has been serviced.
To enable the transmit complete interrupt, set TXIE
(EIE<3>).