Datasheet

 2010 Microchip Technology Inc. DS39935C-page 139
ENC424J600/624J600
REGISTER 16-1: PHCON2: PHY CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
r r EDPWRDN r EDTHRES r r r
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0
r r r r r FRCLNK EDSTAT r
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
Reserved: Write as ‘0’, ignore on read
bit 13
EDPWRDN: Energy Detect Power-Down Enable bit
1 = Energy detect power-down enabled. PHY automatically powers up and down based on the state
of EDSTAT.
0 = Energy detect power-down disabled. Use this setting for maximal compatibility.
bit 12
Reserved: Write as ‘0’, ignore on read
bit 11
EDTHRES: Energy Detect Threshold Control bit
1 = Less energy is required to wake the PHY from energy detect power-down
0 = Normal energy detect threshold
bit 10-3
Reserved: Write as ‘0’, ignore on read
bit 2
FRCLNK: Force Link Control bit
1 = Force immediate link up, even when no link partner is present (100 Mbps operation only)
(1)
0 = Normal operation
bit 1
EDSTAT: Energy Detect Status bit
1 = Energy detect circuit has detected energy on the TPIN+/- pins within the last 256 ms
0 = No energy has been detected on the TPIN+/- pins within the last 256 ms
bit 0
Reserved: Write as ‘0’, ignore on read
Note 1: Intended for testing purposes only. Do not use in 10 Mbps operation.