Datasheet

ENC424J600/624J600
DS39935C-page 14  2010 Microchip Technology Inc.
2.7.1 SPI
When enabled, the SPI interface is implemented with
four pins:
•CS
•SO
•SI
•SCK
All four of these pins must be connected to use the SPI
interface.
The CS
, SI and SCK input pins are 5V tolerant. The SO
pin is also 5V tolerant when in a high-impedance state.
SO is always high-impedance when CS is connected to
logic high (i.e., chip not selected).
When the SPI interface is enabled, all PSP interface
pins (except PSPCFG2 and PSPCFG3 on
ENC624J600 devices) are unused. They are placed in
a high-impedance state and their input buffers are dis-
abled. For best ESD performance, it is recommended
that the unused PSP pins be tied to either V
SS or VDD.
However, these pins may be left floating if it is desirable
for board level layout and routing reasons.
When using an ENC624J600 device in SPI mode, it is
recommended that the PSPCFG2 and PSPCFG3 pins
be tied to either V
SS or any logic high voltage, and not
be left floating. The particular state used is unimportant.
2.7.2 PSP
Depending on the particular device, the PSP interface
is implemented with up to 34 pins. The interface is
highly configurable to accommodate many different
parallel interfaces; not all available pins are used in
every configuration. Up to 8 different operating modes
are available. These are explained in detail in
Section 5.0 “Parallel Slave Port Interface (PSP)”.
The PSPCFG pins control which parallel interface
mode is used. The values on these pins are latched
upon device power-up in the same manner as the
SPISEL pin. The combinations of V
DD and VSS volt-
ages on the different PSPCFG mode pins determine
the PSP mode according to Table 2-1.
On ENC424J600 devices, only PSP Modes 5 and 6
(8-bit width, multiplexed data and address) are
available. The mode is selected by applying V
SS or
V
DD, respectively, to PSPCFG0.
On ENC624J600 devices, all eight PSP modes are
available and are selected by connecting the
PSPCFG<4:1> pins directly to V
DD or ground. The
mode selection is encoded such that the multiplexed
pin functions, AD14 (on PSPCFG1) and SCK/AL (on
PSPCFG4), are used only in the “don’t care” positions.
Therefore, pull-up/pull-down resistors are not required
for these pins.
All PSP pins, except for AD<15:0>, are inputs to the
ENC624J600 family device and are 5V tolerant. The
AD<15:0> pins are bidirectional I/Os and are 5V
tolerant in Input mode. The pins are always inputs
when the CS signal is low (chip not selected).
Any unused PSP pins are placed in a high-impedance
state. However, it is recommended that they be tied to
either Vss or a logic high voltage and not be left floating.
TABLE 2-1: PSP MODE SELECTION FOR ENC424J600/624J600 DEVICES
Interface
Mode
INT
/SPISEL
PSPCFG
Pins Used
01234
44-Pin
PSP Mode 5 Pull Down 0 ———— AL, CS, RD, WR, AD<14:0>
PSP Mode 6 Pull Down 1 ———— AL, CS, RW
, EN, AD<14:0>
64-Pin
PSP Mode 1 Pull Down —x000 CS, RD, WR, A14:A0, AD<7:0>
PSP Mode 2 Pull Down —x001 CS, RW
, EN, A14:A0, AD<7:0>
PSP Mode 3 Pull Down —x100 CS, RD, WRL, WRH, A<13:0>, AD<15:0>
PSP Mode 4 Pull Down —x101 CS, RW, B0SEL, B1SEL, A<13:0>, AD<15:0>
PSP Mode 5 Pull Down —001x AL, CS, RD, WR, AD<14:0>
PSP Mode 6 Pull Down —101x AL, CS, RW
, EN, AD<14:0>
PSP Mode 9 Pull Down —011x AL, CS, RD, WRL, WRH, AD<15:0>
PSP Mode 10 Pull Down —111x AL, CS, RW
, B0SEL, B1SEL, AD<15:0>
Legend: x = don’t care, 0 = logic low (tied to VSS), 1 = logic high (tied to VDD), — = pin not present