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 2010 Microchip Technology Inc. DS39935C-page 15

ENC424J600/624J600

2.7.3 CS/CS PIN

The chip select functions for the serial and parallel

interfaces are shared on one common pin, CS

/CS. This

pin is equipped with both internal weak pull-up and

weak pull-down resistors. If the SPI interface is

selected (CS

), the pull-up resistor is automatically

enabled and the pull-down resistor is disabled. If the

PSP interface is chosen (CS), the pull-down resistor is

automatically enabled and the pull-up resistor is

disabled. This allows the CS

/CS pin to stay in the

unselected state when not being driven, avoiding the

need for an external board level resistor on this pin.

When enabled by using SPI mode, the internal weak

pull-up only pulls the CS

/CS pin up to approximately

DD-1.1V or around 2.2V at typical conditions without

any loading; it does not pull all the way to V

DD. When

using the PSP interface, the pull-down will be enabled,

which is capable of pulling all the way to V

SS when

unloaded.

2.8 Digital I/O Levels

All digital output pins on ENC424J600/624J600

devices contain CMOS output drivers that are capable

of sinking and sourcing up to 18 mA continuously. All

digital inputs and I/O pins operating as inputs are 5V

tolerant. These features generally mean that the

ENCX24J600 can connect directly to the host

microcontroller without the need of any glue logic.

However, some consideration may be necessary when

interfacing with 5V systems.

Since the digital outputs drive only up to the V

voltage (3.3V nominally), the voltage may not be high

enough to ensure a logical high is detected by 5V

systems which have high input thresholds. In such

cases, unidirectional level translation from the 3.3V

ENCX24J600 up to the 5V host microcontroller may be

needed.

When using the SPI interface, an economical 74HCT08

(quad AND gate), 74ACT125 (quad 3-state buffer) or

other 5V CMOS chip with TTL level input buffers may

be used to provide the necessary level shifting. The

use of 3-state buffers permits easy integration into

systems which share the SPI bus with other devices.

However, users must make certain that the propaga-

tion delay of the level translator does not reduce the

maximum SPI frequency below desired levels.

Figure 2-10 and Figure 2-11 show two example

translation schemes.

When using the PSP interface, eight, or all sixteen of

the ADx pins, may need level translation when perform-

ing read operations on the ENCX24J600. The 8-bit

74ACT245 or 16-bit 74ACT16245 bus transceiver, or

similar devices, may be useful in these situations.

FIGURE 2-10: LEVEL SHIFTING ON THE

SPI INTERFACE USING

AND GATES

FIGURE 2-11: LEVEL SHIFTING ON THE

SPI INTERFACE USING

3-STATE BUFFERS

I/O

SCK

SDO

SDI

INTx

MCU

SCK

INT

/SPISEL

ENCX24J600

CLKOUT

OSC1

3.3V

100





I/O

SCK

SDO

SDI