Datasheet

ENC424J600/624J600
DS39935C-page 22  2010 Microchip Technology Inc.
TABLE 3-3: ENC424J600/624J600 SFR MAP (BASE REGISTER MAP, 16-BIT PSP INTERFACE)
3.2.4.1 PSP Bit Set and Bit Clear Registers
A major difference between the SPI and PSP memory
maps is the inclusion of companion Bit Set and Bit
Clear registers for many of the E registers. Since the
PSP interface allows direct access to memory
locations, without a command interpreter, there are no
instructions implemented to perform single bit
manipulations. Instead, this interface implements
separate Bit Set and Bit Clear registers, allowing users
to individually work with volatile bits (such as interrupt
flags) without the risk of disturbing the values of other
bits. Setting the bit(s) in one of these registers sets or
clears the corresponding bit(s) in the base register.
In the PSP interface, Bit Set and Bit Clear registers are
located in different areas of the addressable memory
space from their corresponding “base” SFRs. The
address of the registers is always at a fixed offset from
their corresponding base register. For the 8-bit interface,
the offset is 100h (Set) or 180h (Clear). For the 16-bit
interface, the offset is 80H (Set) or C0 (Clear).
Symbolically, the names of the companion registers are
the names of the base registers, plus the suffix form
“-SET” (or “-SETH/SETL”) for Bit Set registers and
“-CLR” (“-CLRH/CLRL”) for Bit Clear registers.
Most SFRs have their own pair of Bit Set and Bit Clear
registers. However, these SFRs do not:
• MAC registers, including MI registers for PHY
access
• Read-only status registers (ERXHEAD, ETXSTAT,
ETXWIRE and ESTAT)
• All of the SRAM Buffer Pointers and data windows
(SFRs located at 7E80h to 7E9Fh in the 8-bit
interface, or 3F40h to 3F4Fh in the 16-bit
interface)
The Bit Set and Bit Clear registers for the 8-bit PSP
interface are listed in Table 3-4 and Table 3-5,
respectively. The registers for the 16-bit interface are
listed together in Table 3-6.
Addr Name Addr Name Addr Name Addr Name Addr Name
3F00 ETXST 3F10 EHT1 3F20 MACON1 3F30 MAADR3 3F40 EGPDATA
3F01 ETXLEN 3F11 EHT2 3F21 MACON2 3F31 MAADR2 3F41 ERXDATA
3F02 ERXST 3F12 EHT3 3F22 MABBIPG 3F32 MAADR1 3F42 EUDADATA
3F03 ERXTAIL 3F13 EHT4 3F23 MAIPG 3F33 MIWR 3F43 EGPRDPT
3F04 ERXHEAD 3F14 EPMM1 3F24 MACLCON 3F34 MIRD 3F44 EGPWRPT
3F05 EDMAST 3F15 EPMM2 3F25 MAMXFL 3F35 MISTAT 3F45 ERXRDPT
3F06 EDMALEN 3F16 EPMM3 3F26 Reserved 3F36 EPAUS 3F46 ERXWRPT
3F07 EDMADST 3F17 EPMM4 3F27 Reserved 3F37 ECON2 3F47 EUDARDPT
3F08 EDMACS 3F18 EPMCS 3F28 Reserved 3F38 ERXWM 3F48 EUDAWRPT
3F09 ETXSTAT 3F19 EPMO 3F29 MICMD 3F39 EIE 3F49 Reserved
3F0A ETXWIRE 3F1A ERXFCON 3F2A MIREGADR 3F3A EIDLED 3F4A Reserved
3F0B EUDAST 3F1B EUDAST 3F2B EUDAST 3F3B EUDAST 3F4B Reserved
3F0C EUDAND 3F1C EUDAND 3F2C EUDAND 3F3C EUDAND 3F4C Reserved
3F0D ESTAT 3F1D ESTAT 3F2D ESTAT 3F3D ESTAT 3F4D Reserved
3F0E EIR 3F1E EIR 3F2E EIR 3F3E EIR 3F4E Reserved
3F0F ECON1 3F1F ECON1 3F2F ECON1 3F3F ECON1 3F4F
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