Datasheet

ENC424J600/624J600
DS39935C-page 24  2010 Microchip Technology Inc.
TABLE 3-5: ENC424J600/624J600 SFR MAP (CLR REGISTER MAP, 8-BIT PSP INTERFACE)
Bit Clear Registers (7F80h to 7FFFh)
(1)
Addr Name Addr Name Addr Name Addr Name
7F80 ETXSTCLRL 7FA0 EHT1CLRL 7FC0 Reserved 7FE0 Reserved
7F81 ETXSTCLRH 7FA1 EHT1CLRH 7FC1 Reserved 7FE1 Reserved
7F82 ETXLENCLRL 7FA2 EHT2CLRL 7FC2 Reserved 7FE2 Reserved
7F83 ETXLENCLRH 7FA3 EHT2CLRH 7FC3 Reserved 7FE3 Reserved
7F84 ERXSTCLRL 7FA4 EHT3CLRL 7FC4 Reserved 7FE4 Reserved
7F85 ERXSTCLRH 7FA5 EHT3CLRH 7FC5 Reserved 7FE5 Reserved
7F86 ERXTAILCLRL 7FA6 EHT4CLRL 7FC6 Reserved 7FE6 Reserved
7F87 ERXTAILCLRH 7FA7 EHT4CLRH 7FC7 Reserved 7FE7 Reserved
7F88
— 7FA8 EPMM1CLRL 7FC8 Reserved 7FE8 Reserved
7F89
— 7FA9 EPMM1CLRH 7FC9 Reserved 7FE9 Reserved
7F8A EDMASTCLRL 7FAA EPMM2CLRL 7FCA Reserved 7FEA Reserved
7F8B EDMASTCLRH 7FAB EPMM2CLRH 7FCB Reserved 7FEB Reserved
7F8C EDMALENCLRL 7FAC EPMM3CLRL 7FCC Reserved 7FEC EPAUSCLRL
7F8D EDMALENCLRH 7FAD EPMM3CLRH 7FCD Reserved 7FED EPAUSCLRH
7F8E EDMADSTCLRL 7FAE EPMM4CLRL 7FCE Reserved 7FEE ECON2CLRL
7F8F EDMADSTCLRH 7FAF EPMM4CLRH 7FCF Reserved 7FEF ECON2CLRH
7F90 EDMACSCLRL 7FB0 EPMCSCLRL 7FD0 Reserved 7FF0 ERXWMCLRL
7F91 EDMACSCLRH 7FB1 EPMCSCLRH 7FD1 Reserved 7FF1 ERXWMCLRH
7F92
— 7FB2 EPMOCLRL 7FD2 Reserved 7FF2 EIECLRL
7F93
— 7FB3 EPMOCLRH 7FD3 Reserved 7FF3 EIECLRH
7F94
— 7FB4 ERXFCONCLRL 7FD4 Reserved 7FF4 EIDLEDCLRL
7F95
— 7FB5 ERXFCONCLRH 7FD5 Reserved 7FF5 EIDLEDCLRH
7F96 EUDASTCLRL 7FB6 EUDASTCLRL 7FD6 EUDASTCLRL 7FF6 EUDASTCLRL
7F97 EUDASTCLRH 7FB7 EUDASTCLRH 7FD7 EUDASTCLRH 7FF7 EUDASTCLRH
7F98 EUDANDCLRL 7FB8 EUDANDCLRL 7FD8 EUDANDCLRL 7FF8 EUDANDCLRL
7F99 EUDANDCLRH 7FB9 EUDANDCLRH 7FD9 EUDANDCLRH 7FF9 EUDANDCLRH
7F9A
—7FBA—7FDA—7FFA—
7F9B
—7FBB—7FDB— 7FFB —
7F9C EIRCLRL 7FBC EIRCLRL 7FDC EIRCLRL 7FFC EIRCLRL
7F9D EIRCLRH 7FBD EIRCLRH 7FDD EIRCLRH 7FFD EIRCLRH
7F9E ECON1CLRL 7FBE ECON1CLRL 7FDE ECON1CLRL 7FFE ECON1CLRL
7F9F ECON1CLRH 7FBF ECON1CLRH 7FDF ECON1CLRH 7FFF ECON1CLRH
Note 1: Bit Set and Bit Clear registers are not implemented for the base SFRs located between 7E80h and 7E9Fh.