Datasheet

 2010 Microchip Technology Inc. DS39935C-page 25
ENC424J600/624J600
TABLE 3-6: ENC424J600/624J600 SFR MAP (SET/CLR REGISTER MAP, 16-BIT PSP INTERFACE)
Bit Set Registers (3F80h to 3FBFh)
(1)
Addr Name Addr Name Addr Name Addr Name
3F80 ETXSTSET 3F90 EHT1SET 3FA0 Reserved 3FB0 Reserved
3F81 ETXLENSET 3F91 EHT2SET 3FA1 Reserved 3FB1 Reserved
3F82 ERXSTSET 3F92 EHT3SET 3FA2 Reserved 3FB2 Reserved
3F83 ERXTAILSET 3F93 EHT4SET 3FA3 Reserved 3FB3 Reserved
3F84
— 3F94 EPMM1SET 3FA4 Reserved 3FB4 Reserved
3F85 EDMASTSET 3F95 EPMM2SET 3FA5 Reserved 3FB5 Reserved
3F86 EDMALENSET 3F96 EPMM3SET 3FA6 Reserved 3FB6 EPAUSSET
3F87 EDMADSTSET 3F97 EPMM4SET 3FA7 Reserved 3FB7 ECON2SET
3F88 EDMACSSET 3F98 EPMCSSET 3FA8 Reserved 3FB8 ERXWMSET
3F89
— 3F99 EPMOSET 3FA9 Reserved 3FB9 EIESET
3F8A
— 3F9A ERXFCON 3FAA Reserved 3FBA EIDLEDSET
3F8B EUDASTSET 3F9B EUDASTSET 3FAB EUDASTSET 3FBB EUDASTSET
3F8C EUDANDSET 3F9C EUDANDSET 3FAC EUDANDSET 3FBC EUDANDSET
3F8D
—3F9D—3FAD—3FBD—
3F8E EIRSET 3F9E EIRSET 3FAE EIRSET 3FBE EIRSET
3F8F ECON1SET 3F9F ECON1SET 3FAF ECON1SET 3FBF ECON1SET
Bit Clear Registers (3FC0h to 3FFFh)
(1)
Addr Name Addr Name Addr Name Addr Name
3FC0 ETXSTCLR 3FD0 EHT1CLR 3FE0 Reserved 3FF0 Reserved
3FC1 ETXLENCLR 3FD1 EHT2CLR 3FE1 Reserved 3FF1 Reserved
3FC2 ERXSTCLR 3FD2 EHT3CLR 3FE2 Reserved 3FF2 Reserved
3FC3 ERXTAILCLR 3FD3 EHT4CLR 3FE3 Reserved 3FF3 Reserved
3FC4
— 3FD4 EPMM1CLR 3FE4 Reserved 3FF4 Reserved
3FC5 EDMASTCLR 3FD5 EPMM2CLR 3FE5 Reserved 3FF5 Reserved
3FC6 EDMALENCLR 3FD6 EPMM3CLR 3FE6 Reserved 3FF6 EPAUSCLR
3FC7 EDMADSTCLR 3FD7 EPMM4CLR 3FE7 Reserved 3FF7 ECON2CLR
3FC8 EDMACSCLR 3FD8 EPMCSCLR 3FE8 Reserved 3FF8 ERXWMCLR
3FC9
— 3FD9 EPMOCLR 3FE9 Reserved 3FF9 EIECLR
3FCA
— 3FDA ERXFCONCLR 3FEA Reserved 3FFA EIDLEDCLR
3FCB EUDASTCLR 3FDB EUDASTCLR 3FEB EUDASTCLR 3FFB EUDASTCLR
3FCC EUDANDCLR 3FDC EUDANDCLR 3FEC EUDANDCLR 3FFC EUDANDCLR
3FCD
—3FDD—3FED—3FFD—
3FCE EIRCLR 3FDE EIRCLR 3FEE EIRCLR 3FFE EIRCLR
3FCF ECON1CLR 3FDF ECON1CLR 3FEF ECON1CLR 3FFF ECON1CLR
Note 1: Bit Set and Bit Clear registers are not implemented for the base SFRs located between 3F40h and 3F4Fh.