Datasheet
2010 Microchip Technology Inc. DS39935C-page 29
ENC424J600/624J600
3.3.3 SCANNING A PHY REGISTER
The MAC can be configured to perform automatic
back-to-back read operations on a PHY register. This
can reduce the host controller complexity when
periodic status information updates are desired.
To perform the scan operation:
1. Write the address of the PHY register to read
from into the MIREGADR register. Make sure to
also set reserved bit 8 of this register.
2. Set the MIISCAN (MICMD<1>) bit. The scan
operation begins and the BUSY (MISTAT<0>)
bit is automatically set by hardware. The first
read operation will complete after 25.6 s. Sub-
sequent reads will be done at the same interval
until the operation is cancelled. The NVALID
(MISTAT<2>) bit may be polled to determine
when the first read operation is complete.
After setting the MIISCAN bit, the MIRD register will
automatically be updated every 25.6 s. There is no
status information which can be used to determine
when the MIRD registers are updated. On the SPI or
8-bit PSP interfaces, the host controller can only read
one register location at a time. Therefore, it must not be
assumed that the values of MIRDL and MIRDH were
read from the PHY at exactly the same time.
When the MIISCAN operation is in progress, the host
controller must not attempt to write to MIWR or start an
MIIRD operation. The MIISCAN operation can be
cancelled by clearing the MIISCAN (MICMD<1>) bit
and then polling the BUSY (MISTAT<0>) bit. New
operations may be started after the BUSY bit is cleared.
REGISTER 3-1: MIREGADR: MII MANAGEMENT ADDRESS REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
— — — r r r r r
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — PHREG4 PHREG3 PHREG2 PHREG1 PHREG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-8 Reserved: Write as ‘00001’ (01h)
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 PHREG<4:0>: MII Management PHY Register Address Select bits
The address of the PHY register which MII Management read and write operations will apply to.