Datasheet

ENC424J600/624J600
DS39935C-page 32  2010 Microchip Technology Inc.
3.4 Cryptographic Data Memory
The cryptographic data memory is used to store key
and data information for the Modular Exponentiation,
AES and MD5/SHA-1 hashing engines. The RAM for
these modules is actually implemented inside of the
modules themselves; this allows fast memory access
for the access-intensive encryption engines, as well as
the simultaneous use of more than one module by an
application. This memory is mapped into an area of
address space that is accessible only by the DMA
controller. The host controller must write to the crypto-
graphic data memory by writing data to the 24-Kbyte
SRAM buffer, then using the DMA to copy it into the
security engine. Reading is performed in the opposite
order, using the DMA to copy the data out of the
security engine and into the SRAM buffer.
The mapping of the cryptographic space is shown in
Figure 3-3. For additional information on the crypto-
graphic engines, refer to Section 15.0 “Cryptographic
Security Engines”. For additional information on the
DMA controller, see Section 14.0 “Direct Memory
Access (DMA) Controller”.
FIGURE 3-3: CRYPTOGRAPHIC DATA
MEMORY MAPPING
3.5 SRAM Buffer
The SRAM buffer is a bulk 12K word x 16-bit (24 Kbytes)
memory, used for TX/RX packet buffering and general
purpose storage by the host microcontroller. In most
cases, the memory is accessed using a byte-oriented
interface, so the memory can normally be thought of as
a simple 24-Kbyte memory buffer divided into a general
purpose/TX area and an RX area (Figure 3-4).
FIGURE 3-4: SRAM BUFFER
ORGANIZATION
Ethernet communications on 10Base-T and
100Base-TX networks occur at a fixed speed of
10 Mbps or 100 Mbps, respectively. Intra-byte gaps are
not allowed. This requires the host controller to build
outbound transmit frames in their entirety in the SRAM
buffer before the hardware is allowed to begin trans-
mission. Similarly, when receiving packets, the buffer
provides space for the hardware to write the incoming
packet without forcing the host microcontroller to
immediately read and process the packet.
After the part exits Reset, the entire buffer is accessible
by the host controller, regardless of other transmit,
receive or DMA operations that may simultaneously
also be accessing the general purpose or receive
buffer memory.
Exponent (E)
(up to 1024 bits)
DMA Pointers
Data/Result (X/Y)
(up to 1024 bits)
Modulus (M)
(512, 768 or 1024 bits)
Unimplemented
7800h
787Fh
7880h
78FFh
7900h
797Fh
Data In
(512 bits)
Initialization Vector/State In
(160 bits)
Length State In
(55 bits)
7A00h
7A3Fh
7A40h
7A53h
7A54h
7A5Bh
Digest/State Out
(128 or 160 bits)
7A70h
7A83h
Length State Out (55 bits)
7A84h
7A8Bh
Unimplemented
Encryption Key
(128, 192 or 256 bits)
7C00h
7C1Fh
Text A In/Out (128 bits)
7C20h
7C2Fh
Text B In/Out (128 bits)
7C30h
7C3Fh
XOR Out (128 bits)
7C40h
7C4Fh
Modular ExponentiationMD5/SHA-1 HashAES
General Purpose
Buffer
0000h
5FFFh
Circular RX FIFO
Buffer
ERXST
ERXST – 1