Datasheet

 2010 Microchip Technology Inc. DS39935C-page 41
ENC424J600/624J600
4.3 Single Byte Instructions
All single byte instructions are designed to perform a
simple command that affects the ENCX24J600
device’s state. In most cases, they set or clear a small
number of control bits which would otherwise require
one or more N-byte opcodes to perform. None of these
instructions return any data to the host microcontroller.
Figure 4-1 shows the timing relationships for performing
a single byte operation. The opcode (‘11xxxxx0’) is
presented on the device’s SI pin starting with the Most
Significant bit of the opcode; the Least Significant bit is
always ‘0’. The SO pin is actively driven with
indeterminate ‘1’s or ‘0’s while the CS
pin is driven low.
It continues to be driven until the CS
pin is returned high.
Because all single byte instructions are fixed length
with no optional parameters, it is possible to execute
any instruction immediately following the execution of
any single byte instruction without deasserting the chip
select line in between.
If the CS
control signal is deactivated before the 8th bit
of the opcode is sent to the ENCX24J600, indeterminate
results will occur. In some cases, the instruction is
executed or partially executed. To avoid this, it is recom-
mended that a single byte instruction should not be
interrupted. If it is unavoidable that an instruction gets
partially executed, have the application later reissue the
same instruction and let it complete to place the device
into a known state.
There are a total of 20 single byte opcodes, which are
listed in Table 4-2. All single byte opcodes will operate
regardless of which SFR bank is selected at the time.
Those opcodes that affect multiple bits, or affect SFR
addressing, are detailed below.
4.3.1 BxSEL OPCODES
The bank select opcodes, B0SEL, B1SEL, B2SEL and
B3SEL, switch the SFR bank to Bank 0, Bank 1, Bank 2
or Bank 3, respectively. The updated bank select state
is saved internally inside the ENCX24J600 in volatile
memory. Firmware can retrieve the currently selected
SFR bank state by using the Read Bank Select
(RBSEL) opcode.
The bank select opcodes are needed to access most
SFR addresses when using the RCR, WCR, BFS and
BFC instructions. These are discussed in more detail in
Section 4.6 “N-Byte Instructions”.
Upon device power-up or System Reset, Bank 0 is
automatically selected. After Reset, hardware does not
modify the bank state again. Any value programmed by
a BxSEL opcode is retained until the next BxSEL
opcode is executed or a System Reset is issued.
4.3.2 FC (FLOW CONTROL) OPCODES
The flow control opcodes, FCDISABLE, FCSINGLE,
FCMULTIPLE and FCCLEAR, all modify the device’s
Flow Control mode by changing the values of the
FCOP<1:0> bits (ECON1<7:6>). These opcodes
execute regardless of the currently selected SFR bank.
For more information on flow control operation, see
Section 11.0 “Flow Control”.
4.3.3 DMA OPCODES
The DMA opcodes, DMASTOP, DMACKSUM, DMACKSUMS,
DMACOPY and DMACOPYS, modify the operation of the
device’s DMA controller, all by simultaneously changing
the values of the DMAST, DMACPY, DMACSSD and
DMANOCS control bits (ECON1<5:2>). For more infor-
mation on DMA operation, see Section 14.0 “Direct
Memory Access (DMA) Controller”.
FIGURE 4-1: SINGLE BYTE INSTRUCTION TIMING
CS
SCK
SI
SO x x x x x x x xHi-Z Hi-Zx
1 2 3 4 5 6 7 8
Opcode
1 1 c5 c4 c3 c2 c1 0