Datasheet

 2010 Microchip Technology Inc. DS39935C-page 45
ENC424J600/624J600
4.6 N-Byte Instructions
N-byte instructions make up the most versatile class of
SPI commands, as they can read or write to any
addressable SFR or SRAM space. Their name comes
from their variable length nature; they require a mini-
mum of two bytes, but can take an indefinite number of
bytes of data argument, or return an unlimited number
of output bytes. This makes them useful for reading or
writing entire arrays of data to or from the SRAM buffer.
Since these instructions are of an intrinsically variable
length, no other opcode may follow any N-byte
instruction until the CS
line is driven high. Driving CS
high terminates the instruction and then places the SO
pin in a high-impedance state.
The format of the N-byte instructions differs depending
on if a read versus a write command is executed, and
if a banked SFR, unbanked SFR or SRAM location is
accessed. The differences are discussed in the
following sections.
4.6.1 BANKED SFR OPERATION
The N-byte Banked SFR instructions are WCR, RCR, BFS
and BFC. These instructions depend on the use of the
appropriate BxSEL instructions to select the proper SFR
bank prior to their execution. Because of this, they
cannot be used for the unbanked SFR space (80h
through 9Fh).
Figure 4-5 shows the timing relationships for these
operations. Like all other opcodes, data must be
presented on the SI pin, MSb first. For all banked
instructions, the first byte of data must be the opcode,
comprised of a 3-bit prefix designating the instruction
and a 5-bit banked SFR address. If the instruction is a
write or bit field set/clear opcode, the next bytes are the
data or bit mask to be written. For read instructions, the
next bytes on the SI pin are “don’t care”.
For write and bit field set/clear instructions, the SO pin
is actively driven with indeterminate ‘1’s or ‘0’s while
the CS
pin is driven low. For read instructions, indeter-
minate data is clocked out on SO during SCK clocks,
1 through 8. Starting with the 9th clock, valid data is
clocked out byte-wise on SO, MSb first.
As long as the CS
pin is held low, clocks on SCK are
provided and data is presented on SI, the instruction
continues to execute indefinitely, automatically incre-
menting to the next register address in the SFR Bank
and writing data from SI to, or outputting data on SO
from, subsequent registers. When the end of a bank is
reached, the address automatically wraps back to the
beginning (00h) of the bank and continues; the
selected bank does not change.
FIGURE 4-5: N-BYTE SPI INSTRUCTION TIMING (BANKED SFR OPERATIONS)
CS
SCK
SI
SO x x x x x x x xHi-Z
d5 d4 d3 d2 d1d6d7 d0
x x x
D0a4 a3 a2 D7 D6 D5 D4 D3 D2 D1
x x x x x x x x x x x x x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Opcode w/SFR Address
Write 1st Byte
Write 2nd Byte
(optional)
25 26 27
D7 D6 D5
x x x
Additional
c7 c6 c5 a1 a0
CS
SCK
SI
SO x x x x x x x x
Hi-Z
D7 D6 D5
a4 a3 a2
d7 d6 d5 d4 d3 d2 d1 d0 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Read 1st Byte
Read 2nd Byte
(optional)
25 26 27
D7 D6 D5
Additional
c7 c6 c5 a1 a0
Opcode w/SFR Address
Write Operation
Read Operation