Datasheet
2010 Microchip Technology Inc. DS39935C-page 49
ENC424J600/624J600
4.6.3 SRAM BUFFER OPERATIONS
The six N-byte SRAM instructions function in a similar
manner to the banked SFR instructions, in that they use
a single byte opcode to define the operation and target
register. In terms of timing, they are virtually identical, as
shown in Figure 4-7.
Like all other opcodes, data is presented on the SI pin,
MSb first. For all instructions, the first byte of data is the
opcode. If the instruction is a write opcode, the next
bytes are the data to be written. For read instructions,
the next bytes are don’t cares.
For write instructions, the SO pin is actively driven with
indeterminate ‘1’s or ‘0’s while the CS
pin is driven low.
For read instructions, random data is clocked out on
SO during SCK clocks, 1 through 8. Starting with the
9th clock, data is clocked out byte-wise on SO, MSb
first.
As long as the CS
pin is held low, the instruction
continues to execute, automatically incrementing to the
next SRAM address according to the pointer wrapping
rules described in Section 3.5.5 “Indirect SRAM Buffer
Access”. The associated read or write pointer SFRs are
automatically updated for each 8 SCK clocks. To
terminate the read or write operation, the CS
signal must
be returned high.
There are 6 instructions divided equally between read
and write instructions. They are summarized in
Table 4-6.
FIGURE 4-7: N-BYTE SPI OPCODE (SRAM BUFFER OPERATIONS)
CS
SCK
SI
SO x x x x x x x x
Hi-Z
d5 d4 d3 d2 d1d6d7 d0
x x x
D0c4 c3 c2 D7 D6 D5 D4 D3 D2 D1
x x x x x x x x x x x x x
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Opcode Write 1st Byte
Write 2nd Byte
(optional)
25 26 27
D7 D6 D5
x x x
Additional
0 0 1 10
CS
SCK
SI
SO x x x x x x x x
Hi-Z
D7 D6 D5
c4 c3 c2
d7 d6 d5 d4 d3 d2 d1 d0 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Opcode
Read 1st Byte
Read 2nd Byte
(optional)
25 26 27
D7 D6 D5
Additional
0 0 1 0 0
Write Operation
Read Operation