Datasheet

 2010 Microchip Technology Inc. DS39935C-page 53
ENC424J600/624J600
5.2.5 PERFORMANCE
CONSIDERATIONS
When using a 16-bit data bus width, all registers and
direct access to SRAM can be accomplished through
16-bit accesses. Therefore, these modes are poten-
tially twice as fast as their 8-bit equivalent parallel
mode. However, accesses through the
hardware-managed SRAM read/write registers,
EGPDATA, ERXDATA and EUDADATA, are always
8-bit regardless of the interface used. Therefore, in
many applications, it will not be practically feasible to
transfer 16 bits of meaningful data for all bus transfer
cycles.
When reading from the EGPDATA, ERXDATA and
EUDADATA registers on an interface with a multi-
plexed address bus, it is possible to latch the address
only once and then perform back-to-back reads or
writes without performing additional address latch
cycles. This can provide a significant performance
improvement when sequentially reading or writing an
array of data to/from the RAM. Due to this benefit, 8-Bit
Multiplexed modes (Modes 5 and 6) approach the
theoretical performance of the Demultiplexed PSP
Modes 1 and 2.
5.3 PSP Modes
The eight PSP modes are selected using the PSPCFG
pins. The address/data bus and port control connec-
tions differ between the modes, sometimes
significantly, as do the timing relationships between
address/data and control signals. Each of the modes is
described in detail in the following sections.
5.3.1 MODE 1
PSP Mode 1 is an 8-bit, fully demultiplexed mode that
is available on 64-pin devices only. The parallel inter-
face consists of 8 bi-directional data pins (AD<7:0>)
and 9 to 15 separate address pins (A<14:0>). To select
PSP Mode 1, tie PSPCFG2, PSPCFG3 and PSPCFG4
to V
SS. Figure 5-1 shows the connections required.
This mode uses active-high Read and Write strobes
(RD and WR) in conjunction with a Chip Select (CS)
signal. These three pins allow the host to select the
device, then signal when a read operation is desired or
when valid data is being presented to be written. The
AD<7:0> pins stay in a high-impedance state any time
CS or RD is low.
To perform a read operation:
1. Raise the CS line (if connected to the host).
2. Present the address to be read onto the address
bus.
3. Raise the RD strobe and wait the required time
for the access to occur.
When RD is raised high, the data bus begins to drive
out indeterminate data for a brief period, then switches
to the correct read data after the appropriate read
access time has elapsed. When the RD strobe is
lowered, AD<7:0> return to a high-impedance state.
To perform a write operation:
1. Raise the CS line (if connected to the host).
2. Present the address onto the address bus.
3. Present the data on the data bus.
4. Strobe the WR signal high and then low.
For proper operation, do not raise RD and WR
simultaneously while the ENCX24J600 is selected.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-2 and Figure 5-3,
respectively.