Datasheet

 2010 Microchip Technology Inc. DS39935C-page 59
ENC424J600/624J600
5.3.4 MODE 4
PSP Mode 4 is also a 16-bit, fully demultiplexed mode
that is available in 64-pin devices only. When using
PSP Mode 4, the parallel interface consists of
16 bidirectional data pins (AD<15:0>) and 8 to 14 sep-
arate address pins (A<13:0>). To select PSP Mode 4,
tie PSPCFG2 and PSPCFG4 to V
DD, while connecting
PSPCFG3 to V
SS. Figure 5-10 shows the connections
required.
This mode uses a combined Read/Write (R/W
) select,
two Byte Select (B0SEL and B1SEL) lines and a sepa-
rate Chip Select (CS) signal. These four pins allow the
host to select the device, indicate whether a read or
write operation is desired and signal when valid data is
being presented for writing on either the low byte, high
byte or both.
A logic-high signal on R/W
indicates that a read opera-
tion is to be performed when either the B0SEL or
B1SEL strobe is asserted, while a logic low signal
indicates that a write operation is to be performed. The
state of R/W
only affects the data bus state when either
B0SEL or B1SEL is active. When CS is driven low, R/W
is driven low, or both B0SEL and B1SEL are driven low
and the data bus stays in a high-impedance state.
To perform a read operation:
1. Raise the CS line (if connected to the host).
2. Raise the R/W
signal.
3. Present the address to be read onto the address bus.
4. Raise one or both byte select strobes.
When either BxSEL pin is raised high, the data bus
begins driving out indeterminate data for a brief period,
then switches to the correct read data after the appro-
priate read access time has elapsed. When B0SEL and
B1SEL are both low, the data bus pins return to a
high-impedance state.
The device always outputs a full 16 bits of data for each
read request, even if only one byte select is strobed. If
only 8 bits of data are required, read the data from the
correct pins (AD<15:8> or AD<7:0>) and discard the
remaining byte.
To perform a write operation:
1. Raise the CS line (if connected to the host).
2. Lower R/W
.
3. Present the address onto the address bus.
4. If writing to the low byte of the memory location,
present the data on the AD<7:0>; then strobe
B0SEL high, then low.
5. If writing to the high byte, present the data on
AD<15:8> and strobe B1SEL.
6. If writing a whole word, strobe both B0SEL and
B1SEL simultaneously.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-11 and Figure 5-12,
respectively.
FIGURE 5-10: DEVICE CONNECTIONS FOR PSP MODE 4
Host MCU ENC624J600
CS
(1)
R/W
100 k
B0SEL
A<13:8>
(3)
A<7:0>
AD<15:0>
INT
/SPISEL
PMCSx
PMRD/PMWR
PMENB0
PMA<13:8>
PMA<7:0>
PMD<15:0>
INTx
(4)
6
8
16
PSPCFG2
PSPCFG3
PSPCFG4
B1SEL
(2)
PMENB1
(2)
+3.3V
Note 1: Use of the CS strobe from the controller is optional. If not used, tie CS to VDD.
2: B0SEL and B1SEL may optionally be tied together to form a 16-bit write strobe. See Section 5.2.3 “Write
Select Pins”
for details.
3: Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to VDD when only indirect
addressing is desired.
4: Use of the external interrupt signal to the controller is optional.