Datasheet
ENC424J600/624J600
DS39935C-page 64 2010 Microchip Technology Inc.
5.3.6 MODE 6
PSP Mode 6 is also an 8-bit, partially multiplexed mode
that is available on all devices. The parallel interface
consists of 8 multiplexed address and data pins
(AD<7:0>), plus one required high address bit (AD8)
and 6 optional address-only pins (AD<14:9>).
Selecting PSP Mode 6 differs between 44-pin and
64-pin devices, as shown in Figure 5-16. For the 44-pin
ENC424J600, tie PSPCFG0 to V
DD. For the 64-pin
ENC624J600, tie PSPCFG1 and PSPCFG3 to V
DD,
and PSPCFG2 to V
SS.
This mode uses a combined Read/Write (R/W
) select,
an Enable (EN) strobe and separate Chip Select (CS)
and Address Latch (AL) lines. These four pins allow the
host to select the device, latch an address, select either
a read or write operation, then assert the Enable pin
when a read is requested or the data to be written is
valid. For proper operation, do not assert EN and AL
simultaneously while the ENCX24J600 is selected.
AD<14:8> are used as address inputs only, and are
therefore, always left in a high-impedance state. When
CS, R/W
or EN is driven low, the multiplexed AD<7:0>
pins stay in a high-impedance state.
To perform a read operation:
1. Raise CS (if connected to the host).
2. Present the address to read from on AD<14:0>.
3. Strobe AL high and then low.
4. Set the host controller’s AD<7:0> bus pins as
inputs.
5. Raise R/W
.
6. Raise the EN strobe.
The AD<7:0> bus begins driving out indeterminate data
for a brief period, then switches to the correct read data
after the appropriate read access time has elapsed.
When EN is lowered, the multiplexed AD<7:0> pins
return to a high-impedance state.
To perform a write operation:
1. Raise CS (if connected to the host).
2. Present the address to write to on AD<14:0>.
3. Strobe AL.
4. Lower R/W
.
5. Change the data on AD<7:0> from the lower
address byte to the data to be written.
6. Strobe EN high, then low.
If a subsequent read or write of the same memory
address is desired, it is possible to restrobe EN without
going through another address latch cycle.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-17 and Figure 5-18,
respectively.