Datasheet

 2010 Microchip Technology Inc. DS39935C-page 73
ENC424J600/624J600
7.0 RESET
ENC424J600/624J600 differentiates between five
types of Resets:
• Power-on Reset (POR)
• System Reset
• Transmit Only Reset
• Receive Only Reset
• PHY Subsystem Reset
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 7-1.
7.1 Power-on Reset
Power-on Reset occurs when VDD rises above VPOR.
This allows the device to start in the initialized state
when V
DD is adequate for the device’s digital logic to
operate correctly. The POR circuitry is always enabled.
To ensure proper POR operation, the application circuit
must meet the specified minimum rise rate of V
DD
(SVDD, DC parameter D003).
After a Power-on Reset, the contents of the SRAM buffer
and cryptographic memories are unknown. However, all
registers will be loaded with their specified Reset values.
The PHY and other logic should still not be accessed
immediately after the POR. See
Section 8.1 “Reset”
for the recommended Reset procedure.
7.2 System Reset
A System Reset reverts all registers back to their
default Reset values, with the exception of
COCON<3:0> (ECON2<11:8>), which controls the
frequency output on CLKOUT. All transmit, receive,
MAC, PHY, DMA and cryptographic logic are reset.
Additionally, if the SPI interface is used, the current
internal bank selection is reset to Bank 0. The packet
buffer, cryptographic memories and the PSP address
latch used in Multiplexed Parallel modes are unaffected
by a System Reset.
To initiate a System Reset, set the ETHRST bit
(ECON2<4>). The bit is automatically cleared by
hardware. After setting ETHRST, a delay of 25
s is
required before the ENCX24J600 can be accessed
again through the SPI or PSP interfaces. Additionally,
all PHY registers and status bits derived from the PHY
should not be accessed or used for an additional period
of 256
s.
A System Reset does not cause the SPISEL and
PSPCFGx pin states to be relatched. Therefore, the cur-
rently selected controller interface remains available
after issuing a System Reset and waiting the required
25
s.
FIGURE 7-1: ON-CHIP RESET CIRCUIT
POR
Reset SFRs and
Reset TX
Reset RX
Transmit Reset
Receive Reset
System Reset
(ETHRST)
Reset I/O Interface
and CLKOUT
Reset PHY
PHY Reset
(TXRST)
(RXRST)
(PRST)
SPI Bank Select