Datasheet

 2010 Microchip Technology Inc. DS39935C-page 77
ENC424J600/624J600
REGISTER 8-1: ECON2: ETHERNET CONTROL REGISTER 2
R/W-1 R/W-1 R/W-0 R/W-0 R/W-1
(1)
R/W-0
(1)
R/W-1
(1)
R/W-1
(1)
ETHEN STRCH TXMAC SHA1MD5 COCON3 COCON2 COCON1 COCON0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AUTOFC TXRST RXRST ETHRST MODLEN1 MODLEN0 AESLEN1 AESLEN0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15
ETHEN: Ethernet Enable bit
1 = Device is enabled (normal operation)
0 = Device is disabled (reduced power)
bit 14
STRCH: LED Stretching Enable bit
1 = Stretch transmit, receive and collision events on LEDA and LEDB to 50 ms
0 = LEDA and LEDB outputs show real-time status without stretching
bit 13
TXMAC: Automatically Transmit MAC Address Enable bit
1 = MAADR1-MAADR6 registers are automatically inserted into the source address field of all
transmitted packets
0 = No automatic source address insertion
bit 12
SHA1MD5: SHA-1/MD5 Hash Control bit
1 = Hashing engine computes a SHA-1 hash
0 = Hashing engine computes an MD5 hash
bit 11-8
COCON<3:0>: CLKOUT Frequency Control bits
(1)
1111 = 50 kHz nominal ((4 * FOSC)/2000)
1110 = 100 kHz nominal ((4 * FOSC)/1000)
1101 = No output (DC sinking to VSS)
1100 = 3.125 MHz nominal ((4 * FOSC)/32)
1011 = 4.000 MHz nominal ((4 * FOSC)/25)
1010 = 5.000 MHz nominal ((4 * FOSC)/20)
1001 = 6.250 MHz nominal ((4 * FOSC)/16)
1000 = 8.000 MHz nominal ((4 * FOSC)/12.5); duty cycle is not 50%
0111 = 8.333 MHz nominal ((4 * FOSC)/12)
0110 = 10.00 MHz nominal ((4 * FOSC)/10)
0101 = 12.50 MHz nominal ((4 * FOSC)/8)
0100 = 16.67 MHz nominal ((4 * FOSC)/6)
0011 = 20.00 MHz nominal ((4 * FOSC)/5)
0010 = 25.00 MHz nominal ((4 * FOSC)/4)
0001 = 33.33 MHz nominal ((4 * FOSC)/3)
0000 = No output (DC sinking to VSS)
bit 7
AUTOFC: Automatic Flow Control Enable bit
1 = Automatic flow control is enabled
0 = Automatic flow control is disabled
bit 6
TXRST: Transmit Logic Reset bit
1 = Transmit logic is held in Reset. TXRTS (ECON1<1>) is automatically cleared by hardware when
this bit is set.
0 = Transmit logic is not in Reset (normal operation)
Note 1: Reset value on POR events only. All other Resets leave these bits unchanged.