Datasheet

ENC424J600/624J600
DS39935C-page 78  2010 Microchip Technology Inc.
bit 6 RXRST: Receive Logic Reset bit
1 = Receive logic is held in Reset. RXEN (ECON1<0>) is automatically cleared by hardware when this
bit is set.
0 = Receive logic is not in Reset (normal operation)
bit 4
ETHRST: Master Ethernet Reset bit
1 = All TX, RX, MAC, PHY, DMA, modular exponentiation, hashing and AES logic, and registers
(excluding COCON) are reset. Hardware self-clears this bit to ‘
0’. After setting this bit, wait at least
25
s before attempting to read or write to the ENCX24J600 via the SPI or PSP interface.
0 = Device is not in Reset (normal operation)
bit 3-2
MODLEN<1:0>: Modular Exponentiation Length Control bits
11 = Reserved
10 = 1024-bit modulus and operands
01 = 768-bit modulus and operands
00 = 512-bit modulus and operands
bit 1-0
AESLEN<1:0>: AES Key Length Control bits
11 = Reserved
10 = 256-bit key
01 = 192-bit key
00 = 128-bit key
REGISTER 8-1: ECON2: ETHERNET CONTROL REGISTER 2 (CONTINUED)
Note 1: Reset value on POR events only. All other Resets leave these bits unchanged.