Datasheet

 2010 Microchip Technology Inc. DS39935C-page 81
ENC424J600/624J600
bit 2 HFRMEN: Huge Frame Enable bit
1 = Frames of any size will be allowed to be transmitted and received
0 = Frames bigger than MAMXFL will be aborted when transmitted or received
bit 1
Reserved: Write as ‘1’
bit 0
FULDPX: MAC Full-Duplex Enable bit
1 = MAC operates in Full-Duplex mode. For proper operation, the PHY must also be set to Full-Duplex
mode.
0 = MAC operates in Half-Duplex mode. For proper operation, the PHY must also be set to Half-Duplex
mode.
REGISTER 8-3: MACON2: MAC CONTROL REGISTER 2 (CONTINUED)
REGISTER 8-4: MABBIPG: MAC BACK-TO-BACK INTER-PACKET GAP REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
— BBIPG6 BBIPG5 BBIPG4 BBIPG3 BBIPG2 BBIPG1 BBIPG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-0
BBIPG<6:0>: Back-to-Back Inter-Packet Gap Delay Time Control bits
When FULDPX (MACON2<0>) =
1:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble times
minus 3. The recommended setting is 15h which represents the minimum IEEE specified Inter-Packet
Gap (IPG) of 0.96
s (at 100 Mb/s) or 9.6 s (at 10 Mb/s).
When FULDPX (MACON2<0>) =
0:
Nibble time offset delay between the end of one transmission and the beginning of the next in a
back-to-back sequence. The register value should be programmed to the desired period in nibble times
minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet
Gap (IPG) of 0.96
s (at 100 Mb/s) or 9.6 s (at 10 Mb/s).