Datasheet

ENC424J600/624J600
DS39935C-page 90  2010 Microchip Technology Inc.
REGISTER 9-1: ECON1: ETHERNET CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MODEXST HASHEN HASHOP HASHLST AESST AESOP1 AESOP0 PKTDEC
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FCOP1 FCOP0 DMAST DMACPY DMACSSD DMANOCS TXRTS RXEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15
MODEXST: Modular Exponentiation Start bit
1 = Modular exponentiation calculation started/busy; automatically cleared by hardware when done
0 = Modular exponentiation calculation done/Idle
bit 14
HASHEN: MD5/SHA-1 Hash Enable bit
1 = MD5/SHA-1 hashing engine enabled. Data written to the hashing engine by the DMA is added to
the hash.
0 = MD5/SHA-1 hashing engine disabled
bit 13
HASHOP: MD5/SHA-1 Hash Operation Control bit
1 = MD5/SHA-1 hash engine loads the Initial Value (IV) from the hash memory. This mode is typically
used for HMAC hash operations.
0 = Normal MD5/SHA-1 hash operation
bit 12
HASHLST: MD5/SHA-1 Hash Last Block Control bit
1 = The next DMA transfer to the hash engine completes the hash. If needed, padding is automatically
generated and added to the hash.
0 = The next DMA transfer to the hash engine adds data to the hash. Further data additions to the hash
are still possible.
bit 11
AESST: AES Encrypt/Decrypt Start bit
1 = AES encrypt/decrypt operation is started/busy; automatically cleared by hardware when done
0 = AES encrypt/decrypt operation is done/Idle
bit 10-9
AESOP<1:0>: AES Operation Control bits
11 = Reserved
10 = ECB/CBC decrypt
01 = CBC/CFB encrypt
00 = ECB/CFB/OFB encrypt or key initialization
bit 8
PKTDEC: RX Packet Counter Decrement Control bit
1 = Decrement PKTCNT (ESTAT<7:0>) bits by one. Hardware immediately clears PKTDEC to ‘0’,
allowing back-to-back decrement operations.
0 = Leave PKTCNT bits unchanged
bit 7-6
FCOP<1:0>: Flow Control Operation Control/Status bits
When FULDPX (MACON2<0>) =
1:
11 = End flow control by sending a pause frame with 0000h pause timer value; automatically cleared
by hardware when done
10 = Enable flow control by periodically sending pause frames with a pause timer defined by EPAUS
01 = Transmit single pause frame defined by EPAUS; automatically cleared by hardware when done
00 = Flow control disabled/Idle
When FULDPX (MACON2<0>) =
0:
1x, 01 = Enable flow control by continuously asserting backpressure (transmitting preamble)
00 = Flow control disabled/Idle