Datasheet

 2010 Microchip Technology Inc. DS39935C-page 91

ENC424J600/624J600

bit 5 DMAST: DMA Start bit

1 = DMA is started/busy; automatically cleared by hardware when done

0 = DMA is done/Idle

bit 4

DMACPY: DMA Copy Control bit

1 = DMA copies data to memory location at EDMADST

0 = DMA does not copy data; EDMADST is ignored

bit 3

DMACSSD: DMA Checksum Seed Control bit

1 = DMA checksum operations are initially seeded by the one’s complement of the checksum

contained in EDMACS

0 = DMA checksum operations are initially seeded by 0000h

bit 2

DMANOCS: DMA No Checksum Control bit

1 = DMA does not compute checksums; EDMACS remains unchanged

0 = DMA computes checksums; hardware updates EDMACS at the completion of all DMA operations

bit 1

TXRTS: Transmit Request to Send Status/Control bit

1 = Transmit an Ethernet frame; automatically cleared by hardware when done

0 = Transmit logic done/Idle

bit 0

RXEN: Receive Enable bit

1 = Packets which pass the current RX filter configuration are written to the receive buffer

0 = All packets received are ignored