Datasheet

 2010 Microchip Technology Inc. DS39935C-page 93
ENC424J600/624J600
REGISTER 9-3: ESTAT: ETHERNET STATUS REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
INT FCIDLE RXBUSY CLKRDY
r PHYDPX rPHYLNK
bit 15 bit 8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
PKTCNT7 PKTCNT6 PKTCNT5 PKTCNT4 PKTCNT3 PKTCNT2 PKTCNT1 PKTCNT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15
INT: Interrupt Pending Status bit
1 = One of the EIR bits is set and enabled by the EIE register. If INTIE (EIE<15>) is set, the INT pin is
also driven low.
0 = No enabled interrupts are currently pending. The INT pin is being driven high.
bit 14
FCIDLE: Flow Control Idle Status bit
1 = Internal flow control state machine is Idle. It is safe to change the FCOP (ECON1<7:6>) and
FULDPX (MACON2<0>) bits.
0 = Internal flow control state machine is busy. Do not modify the FCOP (ECON1<7:6>) or FULDPX
(MACON2<0>) bits.
bit 13
RXBUSY: Receive Logic Active Status bit
1 = Receive logic is currently receiving a packet. This packet may be discarded in the future if an RX
buffer overflow occurs or a receive filter rejects it, so this bit does not necessarily indicate that an
RX packet pending interrupt will occur.
0 = Receive logic is Idle
bit 12
CLKRDY: Clock Ready Status bit
1 = Normal operation
0 = Internal Ethernet clocks are not running and stable yet. Only the ESTAT and EUDAST registers
should be accessed.
bit 11
Reserved: Ignore on read
bit 10
PHYDPX: PHY Full Duplex Status bit
1 = PHY is operating in Full-Duplex mode
0 = PHY is operating in Half-Duplex mode
bit 9
Reserved: Ignore on read
bit 8
PHYLNK: PHY Linked Status bit
1 = Ethernet link has been established with a remote Ethernet partner
0 = No Ethernet link present
bit 7-0
PKTCNT<7:0>: Receive Packet Count bits
Number of complete packets that are saved in the RX buffer and ready for software processing. Set the
PKTDEC (ECON1<8>) bit to decrement this field.