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ENC424J600/624J600

The ENC424J600/624J600 devices that you have

received conform functionally to the current Device Data

Sheet (DS39935B), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the combined Device/Revision

IDs listed in Table 1. The silicon issues are summarized

in Table 2.

Data Sheet clarifications and corrections start on page 5,

following the discussion of silicon issues.

The silicon revision level can be retrieved by querying

the read-only EIDLEDL register (when using one of the

8-bit interfaces) or the lower byte of the EIDLED

the Device Data Sheet for detailed information on

accessing these registers.

The values for the various ENC424J600/624J600

silicon revisions are shown in Table 1.

TABLE 1:

COMBINED DEVICE/REVISION ID

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon revision

(A2).

Part Number

Value of EIDLEDL or

EIDLED<7:0>

ENC424J600

21h

ENC624J600

ENC424J600/624J600 Silicon Errata

and Data Sheet Clarification

Summary of content (8 pages)

PAGE 1
ENC424J600/624J600 ENC424J600/624J600 Silicon Errata and Data Sheet Clarification The ENC424J600/624J600 devices that you have received conform functionally to the current Device Data Sheet (DS39935B), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the combined Device/Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
ENC424J600/624J600 TABLE 2: SILICON ISSUE SUMMARY Affected Revisions(1) Feature Item Number Receive 1. Rare packet loss following collisions, 10Base-T Half-Duplex mode X PHY Transmit 2. Deviations from MAU Eye Pattern in 10Base-T mode X PHY Transmit 3. Rise time/fall time asymmetry in MLT3 signal X SFR 4. CRYPTEN bit cannot be changed by BFC/BFS/BFCU/BFSU opcodes or EIRSET/EIRCLR registers. X — 5. AES module produces incorrect results.
PAGE 3
ENC424J600/624J600 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A2). 1. Module: PHY (Receive) On rare occasions, in 10Base-T Half-Duplex mode, a collision will cause the immediately following packet to be received incorrectly. This causes the packet to be dropped.
PAGE 4
ENC424J600/624J600 3. Module: PHY (Transmit) For 100Base-TX operation, the IEEE 802.3 specification requires the rise and fall times of the MLT3 signal to match within 0.5 ns, measured over 10 different intervals. The actual rise/fall time symmetry measurements may occasionally be slightly above this level. This issue has no substantial impact on the quality of the transmitted signal and will not impact applications operating in real networks. Work around None. Affected Silicon Revisions A2 X 4.
PAGE 5
ENC424J600/624J600 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39935B): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. No issues. © 2009 Microchip Technology Inc.
PAGE 6
ENC424J600/624J600 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (6/2009) Initial release of this document; issued for revision A2. Includes silicon issues 1 (PHY – Receive), 2-3 (PHY – Transmit), 4 (Memory – SFR) and 5 (AES). DS80477A-page 6 © 2009 Microchip Technology Inc.
PAGE 7
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 8
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