Datasheet

PmodGYRO™ Reference Manual

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Page 2 of 3

Figure 1. Timing diagram.

Correspondingly, if the CS line is left at a high voltage state by an internal pull-up resistor, the I²C mode of the

PmodGYRO is enabled. The on-board chip has two possible slave address in the form of 110100x where x is the

voltage state of the Master-In-Slave-Out (MISO) pin on the SPI header. After the slave address and the read or

write bit has been transmitted and the message was acknowledged, a 7-bit register address can then be

transmitted. The most significant bit (the first bit of the 8-bit of the transfer) indicates if multiple bytes of

information are to be transferred.

An example transfer scheme for a master device reading multiple bytes of data from the PmodGYRO is provided

below:

Master

Slave

Start

Slave address and

Write bit

ACK

Multi-byte bit and

ACK

Restart

Slave address and read

bit

ACK

Data

ACK

Data

ACK

Data

NACK

Stop

Table 1. Example transfer scheme.

Data is recorded and stored within the registers of the L3G4200D in degrees per second (dps). Correspondingly, a

measured value of 360 dps is equivalent to 60 rpm. Users can retrieve data from the PmodGYRO by following the

provided code example.