Datasheet
SSM2518 Data Sheet
Rev. A | Page 26 of 48
REGISTER (REG_MAP) DETAILS
SOFTWARE RESET AND MASTER SOFTWARE POWER-DOWN CONTROL REGISTER
Address: 0x00, Reset: 0x05, Name: Reset_Power_Control
Table 13. Bit Descriptions for Reset_Power_Control
Bits Bit Name Settings Description Reset Access
7 S_RST
Software Reset. Write 1 to reset all internal blocks, including I
2
C registers,
to their initial state.
0x0 RW
0 Normal operation
1 Software reset
6 RESERVED Reserved. 0x0 RW
5 NO_BCLK
Bit Clock Source Selection. Either the MCLK or BCLK pin can be routed
internally to the bit clock.
0x0 RW
0 BCLK pin used as bit clock source. Typical configuration.
1 MCLK pin used as bit clock source. No BCLK pin connection is needed.
[4:1] MCS
Master Clock Select. This must match the ratio between the input MCLK
frequency and the audio sample rate, as shown in Table 11.
0x2 RW
0000 64 × f
S
0001 128 × f
S
0010 256 × f
S
0011 384 × f
S
0100 512 × f
S
0101 768 × f
S
0110 100 × f
S
0111 200 × f
S
1000 400 × f
S
1001 Reserved
0 SPWDN
Software Master Power-Down. This places all blocks, except the I
2
C
interface, into a low power state.
0x1 RW
0 Normal operation
1 Software master power-down