Datasheet

SSM2518 Data Sheet
Rev. A | Page 28 of 48
SERIAL AUDIO INTERFACE AND SAMPLE RATE CONTROL REGISTER
Address: 0x02, Reset: 0x02, Name: Serial_Interface_Sample_Rate_Control
Table 15. Bit Descriptions for Serial_Interface_Sample_Rate_Control
Bits Bit Name Settings Description Reset Access
7 RESERVED Reserved. 0x0 RW
[6:5] SDATA_FMT Serial Data Format. Only required if SAI = 000. 0x0 RW
00 I²S standard; data is delayed by one BCLK cycle
01 Left justified
10 Right justified, 24-bit data
11 Right justified, 16-bit data
[4:2] SAI Serial Audio Interface Format. 0x0 RW
000 I
2
S, left justified, or right justified stereo (depending on SDATA_FMT)
001 2-slot TDM
010 4-slot TDM
011 8-slot TDM
100 16-slot TDM
101 Mono PCM
110 Reserved
111 Reserved
[1:0] FS Manual Sample Rate Selection. Only required if ASR = 1 in Register 0x01. 0x2 RW
00 8 kHz to 12 kHz
01 16 kHz to 24 kHz
10 32 kHz to 48 kHz
11 64 kHz to 96 kHz