Datasheet

Data Sheet SSM2518
Rev. A | Page 35 of 48
POWER AND FAULT CONTROL REGISTER
Address: 0x09, Reset: 0x99, Name: Power_Fault_Control
Table 22. Bit Descriptions for Power_Fault_Control
Bits Bit Name Settings Description Reset Access
[7:6] AR_TIME
Automatic Recovery Delay Time. This determines the amount of time
delay between fault detection and an autorecovery attempt.
0x2 RW
00 10 ms autorecovery delay
01 20 ms autorecovery delay
10 40 ms autorecovery delay
11 80 ms autorecovery delay
5 RESERVED Reserved. 0x0 RW
4 AMP_LPM Class-D Amplifier Low Power Mode. 0x1 RW
0 High performance operation
1 Low power operation
3 DAC_LPM DAC Low Power Mode. In low power mode, the DAC runs at half speed. 0x1 RW
0 Normal operation
1 Low power operation
2 R_PWDN Right Channel Power-Down. 0x0 RW
0 Normal operation
1 Right channel powered down
1 L_PWDN Left Channel Power-Down. 0x0 RW
0 Normal operation
1 Left channel powered down
0 APWDN_EN
Automatic Power-Down Enable. Automatic power-down automatically
puts the IC in a low power state when 2048 consecutive zero input
samples have been received.
0x1 RW
0 Automatic power-down disabled
1 Automatic power-down enabled