Datasheet

Data Sheet SSM2518
Rev. A | Page 7 of 48
DIGITAL TIMING
All timing specifications are given for the default setting (I
2
S mode) of the serial input port.
Table 5.
Limit
Parameter Min Max Unit Description
MASTER CLOCK
t
MP
74 136 ns MCLK period, 256 × f
S
mode (MCS = b0010)
t
MP
148 271 ns MCLK period, 128 × f
S
mode (MCS = b0001)
SERIAL PORT
t
BIL
40 ns BCLK low pulse width
t
BIH
40 ns BCLK high pulse width
t
LIS
10 ns Setup time from LRCLK or SDATA edge to BCLK rising edge
t
LIH
10 ns Hold time from BCLK rising edge to LRCLK or SDATA edge
t
SIS
10 ns SDATA setup time to BCLK rising
t
SIH
10 ns SDATA hold time from BCLK rising
I
2
C PORT
f
SCL
400 kHz SCL frequency
t
SCLH
0.6 μs SCL high
t
SCLL
1.3 μs SCL low
t
SCS
0.6 μs Setup time; relevant for repeated start condition
t
SCH
0.6 μs Hold time; after this period, the first clock is generated
t
DS
100 ns Data setup time
t
SCR
300 ns SCL rise time
t
SCF
300 ns SCL fall time
t
SDR
300 ns SDA rise time
t
SDF
300 ns SDA fall time
t
BFT
0.6 μs Bus-free time (time between stop and start)
Digital Timing Diagrams
t
SIS
t
SIH
t
SIS
t
SIH
t
LIH
t
BP
t
BIH
BCLK
LRCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
I
2
C-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
t
BIL
t
LIS
t
SIS
t
SIH
t
SIS
t
SIH
MSB
MSB
MSB LSB
MSB – 1
10242-002
Figure 2. Serial Input Port Timing
t
SCH
t
SCS
t
BFT
t
SCF
t
DS
t
SCLL
t
SCR
t
SCLH
t
SCH
STOP
CONDITION
START
CONDITION
S
D
A
SCL
10242-003
Figure 3. I
2
C Port Timing