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PmodAMP3™ Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 2 of 3
If JP5 is loaded, I²C is enabled so that the on-board chip can be configured. Consequently, the shorting blocks on
both JP3 and JP4 must be removed so that the SCL and SDA lines are pulled to a logic high voltage state. JP6 sets
the I²C address of the Pmod; both addresses are valid, but a user may want to use one particular address if another
I²C device on the bus is using the other address.
JP5 Unloaded (default Stand-alone mode)
JP5 Loaded (I
2
C Programmable Mode)
Loaded
Unloaded
Loaded
Unloaded
JP2
MCLK-provide own
external MCLK
BCLK-route BCLK
to MCLK input
Don't Care
Don't Care
JP3
I
2
S (Standard)
Left Justified
Prohibited
Required
JP4
256x Fs
384x Fs
Prohibited
Required
JP6
12dB Gain
0dB Gain
ADDR: 0110100[r/w]
ADDR: 0110110[r/w]
Table 1. Connector descriptions.
Note: Both the 0dB and +12dB gain modes are very loud. You should take care to protect both yourself and your
equipment when operating in stand-alone mode. Digilent recommends that you use the programmable mode and
set the gain to -12dB or lower.
The I²C programmable mode is used to set alternate Master Clock (MCLK) and Bit Clock (BCLK) ratios as well as
configure the Dynamic Range Control (DRC). More information about these options is available in our user guide.
To transfer audio data in the I²S audio format, the MCLK, BCLK, the Left/Right Word Clock (LRCLK), and the data
(SDATA) will need to be provided either internally or externally as appropriate. This module is able to receive audio
data anywhere between 8 and 32-bits of resolution. An example timing diagram from Texas Instruments on how
I²S data is to be sent to the module is provided below:
Figure 1. Example I
2
S timing diagram.