Datasheet

 2009-2016 Microchip Technology Inc. DS60001156J-page 101
PIC32MX5XX/6XX/7XX
9.0 PREFETCH CACHE
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1 Features
• 16 fully-associative lockable cache lines
• 16-byte cache lines
• Up to four cache lines allocated to data
• Two cache lines with address mask to hold
repeated instructions
• Pseudo-LRU replacement policy
• All cache lines are software writable
• 16-byte parallel memory fetch
• Predictive instruction prefetch
A simplified block diagram of the Prefetch Cache
module is illustrated in Figure 9-1.
FIGURE 9-1: PREFETCH CACHE MODULE BLOCK DIAGRAM
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS60001119) in the “PIC32
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
CTRL
RDATA
Prefetch
Prefetch
Hit Logic
Cache
Line
Address
Encode
Cache Line
FSM
CTRL RDATA
Tag Logic
Bus Control
Cache Control
Prefetch Control
Hit LRU
Miss LRU
BMX/CPU
BMX/CPU
CTRL
PFM