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ManualsBrandsDIGILENT ManualsDev KitsPCB design board
361362363364365366367368369370
PIC32MX5XX/6XX/7XX
DS60001156J-page 370 2009-2016 Microchip Technology Inc.
FIGURE 32-4: POWER-ON RESET TIMING CHARACTERISTICS
V
DD
V
POR
Note 1:
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(V
DD
< V
DDMIN
).
2:
Includes interval voltage regulator stabilization delay.
SY00
Power-up Sequence
(Note 2)
Internal Voltage Regulator Enabled
(T
PU
)
SY10
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and S
OSC
)
V
DD
V
POR
SY00
Power-up Sequence
(Note 2)
Internal Voltage Regulator Enabled
(T
PU
)
(T
SYSDLY
)
CPU Starts Fetching Code
(Note 1)
(Note 1)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
(T
OST
)
SY02
(T
SYSDLY
)
SY02