Datasheet

PIC32MX5XX/6XX/7XX
DS60001156J-page 434  2009-2016 Microchip Technology Inc.
Oscillator Configuration.......................................................95
Output Compare................................................................185
P
Packaging .........................................................................401
Details .......................................................................403
Marking .....................................................................401
Parallel Master Port (PMP) ...............................................211
PIC32 Family USB Interface Diagram...............................134
PICkit 3 In-Circuit Debugger/Programmer ........................349
Pinout I/O Descriptions (table) ............................................26
Power-on Reset (POR)
and On-Chip Voltage Regulator................................343
Power-Saving Features.....................................................331
CPU Halted Methods ................................................331
Operation .................................................................. 331
with CPU Running.....................................................331
Prefetch Cache .................................................................101
Program Flash Memory
Wait State Characteristics.........................................363
R
Real-Time Clock and Calendar (RTCC)............................221
Register Maps .............................................................55–283
Registers
AD1CHS (ADC Input Select) ....................................239
AD1CON1 (ADC Control 1) ......................................235
AD1CON2 (ADC Control 2) ......................................237
AD1CON3 (ADC Control 3) ......................................238
AD1CSSL (ADC Input Scan Select) .........................240
ALRMDATE (Alarm Date Value)...............................230
ALRMTIME (Alarm Time Value) ...............................229
BMXBOOTSZ (Boot Flash (IFM) Size) .......................61
BMXCON (Bus Matrix Configuration) .........................56
BMXDKPBA (Data RAM Kernel Program
Base Address) ....................................................57
BMXDRMSZ (Data RAM Size) ................................... 60
BMXDUDBA (Data RAM User Data Base Address) ... 58
BMXDUPBA (Data RAM User Program
Base Address) ....................................................59
BMXPFMSZ (Program Flash (PFM) Size) .................. 61
BMXPUPBA (Program Flash (PFM) User Program
Base Address) ....................................................60
CHEACC (Cache Access) ........................................104
CHECON (Cache Control) ........................................103
CHEHIT (Cache Hit Statistics) ..................................109
CHELRU (Cache LRU) .............................................108
CHEMIS (Cache Miss Statistics) ..............................109
CHEMSK (Cache TAG Mask)................................... 106
CHETAG (Cache TAG)............................................. 105
CHEW0 (Cache Word 0)...........................................106
CHEW1 (Cache Word 1)...........................................107
CHEW2 (Cache Word 2)...........................................107
CHEW3 (Cache Word 3)...........................................108
CiCFG (CAN Baud Rate Configuration)....................248
CiCON (CAN Module Control) ..................................246
CiFIFOBA (CAN Message Buffer Base Address) .....273
CiFIFOCINn (CAN Module Message Index Register ‘n’)
278
CiFIFOCONn (CAN FIFO Control Register ‘n’).........274
CiFIFOINTn (CAN FIFO Interrupt Register ‘n’) .........276
CiFIFOUAn (CAN FIFO User Address Register ‘n’)..278
CiFLTCON0 (CAN Filter Control 0)...........................256
CiFLTCON1 (CAN Filter Control 1)...........................258
CiFLTCON2 (CAN Filter Control 2)...........................260
CiFLTCON3 (CAN Filter Control 3)...........................262
CiFLTCON4 (CAN Filter Control 4) .......................... 264
CiFLTCON5 (CAN Filter Control 5) .......................... 266
CiFLTCON6 (CAN Filter Control 6) .......................... 268
CiFLTCON7 (CAN Filter Control 7) .......................... 270
CiFSTAT (CAN FIFO Status).................................... 253
CiINT (CAN Interrupt)............................................... 250
CiRXFn (CAN Acceptance Filter ‘n’)......................... 272
CiRXMn (CAN Acceptance Filter Mask ‘n’) .............. 255
CiRXOVF (CAN Receive FIFO Overflow Status) ..... 254
CiTMR (CAN Timer) ................................................. 254
CiTREC (CAN Transmit/Receive Error Count)......... 253
CiVEC (CAN Interrupt Code).................................... 252
CMSTAT (Comparator Control Register).................. 326
CMxCON (Comparator ’x’ Control)........................... 325
CNCON (Change Notice Control)............................. 166
CVRCON (Comparator Voltage Reference Control) 329
DCHxCON (DMA Channel ’x’ Control) ..................... 124
DCHxCPTR (DMA Channel ’x’ Cell Pointer)............. 131
DCHxCSIZ (DMA Channel ’x’ Cell-Size) .................. 131
DCHxDAT (DMA Channel ’x’ Pattern Data).............. 132
DCHxDPTR (Channel ’x’ Destination Pointer).......... 130
DCHxDSA (DMA Channel ’x’ Destination
Start Address)................................................... 128
DCHxDSIZ (DMA Channel ’x’ Destination Size)....... 129
DCHxECON (DMA Channel ’x’ Event Control)......... 125
DCHxINT (DMA Channel ’x’ Interrupt Control) ......... 126
DCHxSPTR (DMA Channel ’x’ Source Pointer)........ 130
DCHxSSA (DMA Channel ’x’ Source Start Address) 128
DCHxSSIZ (DMA Channel ’x’ Source Size).............. 129
DCRCCON (DMA CRC Control)............................... 121
DCRCDATA (DMA CRC Data)................................. 123
DCRCXOR (DMA CRCXOR Enable) ....................... 123
DDPCON (Debug Data Port Control) ....................... 342
DEVCFG0 (Device Configuration Word 0................. 335
DEVCFG1 (Device Configuration Word 1................. 337
DEVCFG2 (Device Configuration Word 2................. 339
DEVCFG3 (Device Configuration Word 3................. 341
DEVID (Device and Revision ID).............................. 342
DMAADDR (DMA Address)...................................... 120
DMACON (DMA Controller Control)......................... 119
DMASTAT (DMA Status).......................................... 120
EMAC1CFG1 (Ethernet Controller MAC Configuration 1)
306
EMAC1CFG2 (Ethernet Controller MAC Configuration 2)
307
EMAC1CLRT (Ethernet Controller MAC Collision Win-
dow/Retry Limit)................................................ 311
EMAC1IPGR (Ethernet Controller MAC Non-Back-to-
Back Interpacket Gap)...................................... 310
EMAC1IPGT (Ethernet Controller MAC Back-to-Back In-
terpacket Gap).................................................. 309
EMAC1MADR (Ethernet Controller MAC MII Manage-
ment Address) .................................................. 317
EMAC1MAXF (Ethernet Controller MAC Maximum
Frame Length).................................................. 312
EMAC1MCFG (Ethernet Controller MAC MII Manage-
ment Configuration).......................................... 315
EMAC1MCMD (Ethernet Controller MAC MII Manage-
ment Command)............................................... 316
EMAC1MIND (Ethernet Controller MAC MII Manage-
ment Indicators)................................................ 319
EMAC1MRDD (Ethernet Controller MAC MII Manage-
ment Read Data) .............................................. 318
EMAC1MWTD (Ethernet Controller MAC MII Manage-
ment Write Data) .............................................. 318