Datasheet

T/H
8-BIT
SUCCESSIVE
APPROXIMATION
ADC
SCLK
CS
SDATA
CONTROL
LOGIC
V
IN
Copyright © 2016, Texas Instruments Incorporated
12
ADC081S021
SNAS308G –APRIL 2005–REVISED MAY 2016 www.ti.com
Product Folder Links: ADC081S021
Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The ADC081S021 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter core. Simplified schematics of the ADC081S021 in both track and hold
modes are shown in Figure 19 and Figure 18, respectively. In Figure 19, the device is in track mode: switch SW1
connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this
state until CS is brought low, at which point the device moves to hold mode.
8.2 Functional Block Diagram
8.3 Feature Description
The serial interface timing diagram for the ADC is shown in Timing Requirements. CS is chip select, which
initiates conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the
conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is
found as a serial data stream.
Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK are labelled with reference to the falling edge of CS; for example,
the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE and the converter moves from track mode to hold
mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from
hold mode to track mode on the 13th rising edge of SCLK (see Timing Requirements). It is at this point that the
interval for the T
ACQ
specification begins. At least 350 ns must pass between the 13th rising edge of SCLK and
the next falling edge of CS. The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK,
or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time (t
QUIET
) must
be satisfied before bringing CS low again to begin another conversion.
Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading
or trailing zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on
subsequent rising edges of SCLK. The ADC produces three leading zero bits on SDATA, followed by eight data
bits, most significant first. After the data bits, the ADC clocks out four trailing zeros.
If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling
edge of SCLK.
8.3.1 Determining Throughput
Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one
conversion and the start of another. At the maximum specified SCLK frequency, the maximum ensured
throughput is obtained by using a 20 SCLK frame. As shown in Timing Requirements, the minimum allowed time
between CS falling edges is determined by:
1. 12.5 SCLKs for Hold mode.
2. The larger of two quantities: either the minimum required time for Track mode (t
ACQ
) or 2.5 SCLKs to finish
reading the result.