Datasheet

GND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
V
IN
V
A
2
GND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
V
IN
V
A
2
13
ADC081S021
www.ti.com SNAS308G –APRIL 2005–REVISED MAY 2016
Product Folder Links: ADC081S021
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Feature Description (continued)
3. 0, 1/2, or 1 SCLK padding to ensure an even number of SCLK cycles so there is a falling SCLK edge when
CS next falls.
For example, at the fastest rate for this family of parts, SCLK is 20 MHz and 2.5 SCLKs are 125 ns, so the
minimum time between CS falling edges is calculated by Equation 1.
12.5 × 50 ns + 350 ns + 0.5 × 50 ns = 1000 ns (1)
(12.5 SCLKs + t
ACQ
+ 1/2 SCLK) which corresponds to a maximum throughput of 1 MSPS. At the slowest rate for
this family, SCLK is 1 MHz. Using a 20 cycle conversion frame as shown in Timing Requirements yields a 20-μs
time between CS falling edges for a throughput of 50 KSPS. It is possible, however, to use fewer than 20 clock
cycles provided the timing parameters are met. With a 1-MHz SCLK, there are 2500 ns in 2.5 SCLK cycles,
which is greater than t
ACQ
. After the last data bit has come out, the clock needs one full cycle to return to a falling
edge. Thus the total time between falling edges of CS is 12.5 × 1 μs + 2.5 × 1 μs + 1 × 1 μs = 16 μs which is a
throughput of 62.5 KSPS.
8.4 Device Functional Modes
Figure 18 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining
the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-
redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The device moves from hold mode to track mode (Figure 19) on the 13th rising edge of
SCLK.
Figure 18. Hold Mode
Figure 19. Track Mode
8.4.1 Transfer Function
The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB
values. The LSB width for the ADC is V
A
/256. The ideal transfer characteristic is shown in Figure 20. The
transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of V
A
/512. Other
code transitions occur at steps of one LSB.