Datasheet

000...001
000...010
0V
011...111
111...000
000...000
111...111
111...110
ADC CODE
ANALOG INPUT
1 LSB = V
A
/256
1 LSB
+V
A
-1 LSB
||
|
14
ADC081S021
SNAS308G –APRIL 2005–REVISED MAY 2016 www.ti.com
Product Folder Links: ADC081S021
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Device Functional Modes (continued)
Figure 20. Ideal Transfer Characteristic
8.4.2 Modes of Operation
The ADC has two possible modes of operation: normal mode and shutdown mode. The ADC enters normal
mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is
pulled high before the tenth falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains
low. Once in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time
spent in the normal and shutdown modes, a system may trade off throughput for power consumption, with a
sample rate as low as zero.
8.4.2.1 Normal Mode
The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no
power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th
falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device remains in normal
mode, but the current conversion is aborted and the SDATA returns to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles
have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought
high again before the start of the next conversion, which begins when CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after t
QUIET
has
elapsed, by bringing CS low again.
8.4.2.2 Shutdown Mode
Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade
throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second
and tenth falling edges of SCLK, as shown in Figure 21. Once CS has been brought high in this manner, the
device enters shutdown mode, the current conversion is aborted and SDATA enters TRI-STATE. If CS is brought
high before the second falling edge of SCLK, the device does not change mode; this is to avoid accidentally
changing mode as a result of noise on the CS line.