Datasheet
Z2 Z1 Z0 DB7
Zero
Zero Zero Zero
t
QUIET
Track
3 leading zero bits
8 data bits
CS
SCLK
SDATA
1 2 3 4 5 12 13 14 15 16
TRI-STATE
|
|
|
t
SU
t
CL
t
EN
t
CH
t
ACC
t
H
t
DIS
t
CS
Hold
t
ACQ
17 18
19
20
4 trailing zeroes
I
OL
200 PA
I
OH
200 PA
1.6 V
To Output Pin
C
L
25 pF
7
ADC081S021
www.ti.com
SNAS308G –APRIL 2005–REVISED MAY 2016
Product Folder Links: ADC081S021
Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated
(1) Data sheet minimum and maximum specification limits are specified by design, test, or statistical analysis.
(2) Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V.
(3) Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V or 2 V.
(4) t
DIS
is derived from the time taken by the outputs to change by 0.5 V with the timing test circuit. The measured number is then adjusted
to remove the effects of charging or discharging the output capacitance. This means that t
DIS
is the true bus relinquish time, independent
of the bus loading.
7.6 Timing Requirements
The following specifications apply for V
A
= 2.7 V to 5.25 V, GND = 0 V, f
SCLK
= 1.0 MHz to 4.0 MHz, C
L
= 25 pF, f
SAMPLE
= 50
ksps to 200 ksps, and T
A
= –40°C to 85°C (unless otherwise noted).
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
CS
Minimum CS pulse width 10 ns
t
CSSU
CS setup time prior to SCLK falling edge 10 ns
t
CSH
CS hold time after SCLK falling edge 1 ns
t
EN
Delay from CS until SDATA TRI-STATE disabled
(2)
20 ns
t
ACC
Data access time after SCLK falling edge
(3)
V
A
= 2.7 V to 3.6 V 40 ns
V
A
= 4.75 V to 5.25 V 20 ns
t
CL
SCLK low pulse width 0.4 × t
SCLK
ns
t
CH
SCLK high pulse width 0.4 × t
SCLK
ns
t
H
SCLK to data valid hold time
V
A
= 2.7 V to 3.6 V 7 ns
V
A
= 4.75 V to 5.25 V 5 ns
t
DIS
SCLK falling edge to SDATA high impedance
(4)
V
A
= 2.7 V to 3.6 V 6 25 ns
V
A
= 4.75 V to 5.25 V 5 25 ns
t
POWER-UP
Power-up time from full power down T
A
= 25°C 1 µs
Figure 1. Timing Test Circuit
Figure 2. Serial Timing Diagram