Information

Nexys4 DDR™ FPGA Board Reference Manual

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setting (seen in Figure 3) is useful to prevent the FPGA from being configured from any other bitstream source

until a JTAG programming occurs.

Programming the Nexys4 DDR with an uncompressed bitstream using the on-board USB-JTAG circuitry usually

takes around five seconds. JTAG programming can be done using the hardware server in Vivado or the iMPACT tool

included with ISE and the Lab Tools version of Vivado. The demonstration project available at www.digilentinc.com

gives an in-depth tutorial on how to program your board.

3.2 Quad-SPI Configuration

Since the FPGA on the Nexys4 DDR is volatile, it relies on the Quad-SPI flash memory to store the configuration

between power cycles. This configuration mode is called Master SPI. The blank FPGA takes the role of master and

reads the configuration file out of the flash device upon power-up. To that effect, a configuration file needs to be

downloaded first to the flash. When programming a nonvolatile flash device, a bitstream file is transferred to the

flash in a two-step process. First, the FPGA is programmed with a circuit that can program flash devices, and then

data is transferred to the flash device via the FPGA circuit (this complexity is hidden from the user by the Xilinx

tools). This is called indirect programming. After the flash device has been programmed, it can automatically

configure the FPGA at a subsequent power-on or reset event as determined by the mode jumper setting (see

Figure 3). Programming files stored in the flash device will remain until they are overwritten, regardless of power-

cycle events.

Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process

inherent to the memory technology. Once written however, FPGA configuration can be very fast—less than a

second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that

can affect configuration speed. The Nexys4 DDR supports x1, x2, and x4 bus widths and data rates of up to 50 MHz

for Quad-SPI programming.

Quad-SPI programming can be done using the iMPACT tool included with ISE or the Lab Tools version of Vivado.

3.3 USB Host and Micro SD Programming

You can program the FPGA from a pen drive attached to the USB Host port (J5) or a microSD card inserted into J1

by doing the following:

1. Format the storage device (Pen drive or microSD card) with a FAT32 file system.

2. Place a single .bit configuration file in the root directory of the storage device.

3. Attach the storage device to the Nexys4 DDR.

4. Set the JP1 Programming Mode jumper on the Nexys4 DDR to “USB/SD”.

5. Select the desired storage device using JP2.

6. Push the PROG button or power-cycle the Nexys4 DDR.

The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not

built for the proper Artix-7 device will be rejected by the FPGA.

The Auxiliary Function Status, or “BUSY” LED, gives visual feedback on the state of the configuration process when

the FPGA is not yet programmed:

 When steadily lit, the auxiliary microcontroller is either booting up or currently reading the configuration

medium (microSD or pen drive) and downloading a bitstream to the FPGA.

 A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.