Datasheet
Genesys 2 FPGA Board Reference Manual
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Page 10 of 31
6. Push the PROG button or power-cycle the Genesys 2.
The FPGA will automatically configure with the .bit file on the selected storage device. Any .bit files that are not
built for the proper Kintex-7 device will be rejected by the FPGA.
The Auxiliary Function Status or “BUSY” LED (LD11) gives visual feedback on the state of the configuration process
when the FPGA is not yet programmed:
When steadily lit the auxiliary microcontroller is either booting up or currently reading the configuration
medium (microSD or pen drive) and downloading a bitstream to the FPGA.
A slow pulse means the microcontroller is waiting for a configuration medium to be plugged in.
In case of an error during configuration the LED will blink rapidly. It could be that the device plugged in is
not getting recognized, it is not properly formatted or the bitstream is not compatible with the FPGA.
When the FPGA has been successfully configured, the behavior of the LED is application-specific. For example, if a
USB keyboard or mouse is plugged in, a rapid short blink will signal the receipt of an HID input report from
peripheral.
6 Memory
The Genesys 2 board contains two external memories: a 1GiByte volatile DDR3 memory and a 32MiByte non-
volatile serial Flash device. The DDR3 uses two 16-bit wide memory component with industry-standard interface
soldered on the board resulting in a 32-bit data bus. The serial Flash is on a dedicated quad-mode (x4) SPI bus.
6.1 DDR3
The Genesys 2 includes two Micron MT41J256M16HA-107 DDR3 memory component creating a single rank, 32-bit
wide interface. It is routed to a 1.5V-powered HP (High Performance) FPGA bank with 40 ohm controlled single-
ended trace impedance. For data signals 40 ohm DCI terminations in the FPGA are used to match the trace
characteristics. Similarly, on the memory side on-die terminations (ODT) are used for impedance matching.
Address/Control signals are terminated using discrete resistors.
The highest data rate supported is 1800Mbps.
For proper operation of the memory a memory controller and physical layer (PHY) interface needs to be included in the FPGA design. The Xilinx
7-series memory interface solutions core generated by the MIG (Memory Interface Generator) Wizard hides away the complexities of a DDR3
interface. Depending on the tool used (ISE, EDK or Vivado) the MIG Wizard can generate a native FIFO-style or an AXI4 interface to connect to
user logic. This workflow allows the customization of several DDR3 parameters optimized for the particular application.
Table 4 below lists the MIG Wizard settings optimized for the Genesys 2.
Setting
Value
Memory type
DDR3 SDRAM
Max. clock period
1112ps (~900MHz)
Max. data rate
~1800Mbps
Clock ratio
4:1
VCCAUX_IO
2.0V
Memory type
Components
Memory part
MT41J256M16XX-107
Memory voltage
1.5V
Data width
32